Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46219 )
Change subject: mb/facebook/fbg1701: Add VBOOT support ......................................................................
mb/facebook/fbg1701: Add VBOOT support
Add VBOOT support.
Disabled USE_VENDOR_ELTAN when VBOOT is enabled. Add FMD file and split binary into RW and RO region settings.
Signed-off-by: Frans Hendriks fhendriks@eltan.com
Tested on Facebook FBG1701 Signed-off-by: Frans Hendriks fhendriks@eltan.com
Change-Id: I641bca58c0f7c81d5742235c8b2c184d13c00c55 --- M src/mainboard/facebook/fbg1701/Kconfig A src/mainboard/facebook/fbg1701/vboot-rw.fmd 2 files changed, 45 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/46219/1
diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig index d86458f..d6d2a27 100644 --- a/src/mainboard/facebook/fbg1701/Kconfig +++ b/src/mainboard/facebook/fbg1701/Kconfig @@ -20,7 +20,18 @@ select DISABLE_HPET select INTEL_GMA_HAVE_VBT select HAVE_SPD_IN_CBFS - select USE_VENDORCODE_ELTAN + +config USE_VENDORCODE_ELTAN + depends on !VBOOT + default y + +config VBOOT_VBNV_CMOS + depends on VBOOT + default y + +config VBOOT_SLOTS_RW_AB + depends on VBOOT + default n
config ONBOARD_SAMSUNG_MEM bool "Onboard memory manufacturer Samsung" @@ -88,4 +99,16 @@ bool default n
+config FMDFILE + depends on VBOOT + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rw.fmd" + +config RW_REGION_ONLY + depends on VBOOT + default "%/payload logo.bmp %/ramstage vbt.bin %/dsdt.aml config %/postcar" + +config RO_REGION_ONLY + depends on VBOOT + default "spd.bin fsp.bin cpu_microcode_blob.bin" + endif # BOARD_FACEBOOK_FBG1701 diff --git a/src/mainboard/facebook/fbg1701/vboot-rw.fmd b/src/mainboard/facebook/fbg1701/vboot-rw.fmd new file mode 100644 index 0000000..51ee470 --- /dev/null +++ b/src/mainboard/facebook/fbg1701/vboot-rw.fmd @@ -0,0 +1,21 @@ +FLASH 8M { + SI_BIOS@0x200000 0x600000 { + MISC_RW@0x0 0x08000 { + RW_MRC_CACHE@0 0x08000 + } + RW_SECTION_A@0x08000 0x578000 { + VBLOCK_A@0x0 0x10000 + RW_FWID_A@0x10000 0x40 + FW_MAIN_A(CBFS)@0x10040 0x567FC0 + } + WP_RO@0x580000 0x080000 { + RO_SECTION@0x0000 0x80000 { + FMAP@0x0 0x400 + RO_FRID@0xA00 0x40 + RO_FRID_PAD@0xA40 0x5c0 + GBB@0x1000 0x4000 + COREBOOT(CBFS)@0x5000 0x07B000 + } + } + } +}