[coreboot-gerrit] [XS] Change in coreboot[main]: soc/intel/xeon_sp: Handle GPIO SMIs

[Shuo Liu (Code Review)]

Attention is currently required from: Alicja Michalska, Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu.

Shuo Liu has posted comments on this change by Alicja Michalska. ( https://review.coreboot.org/c/coreboot/+/84301?usp=email )

Change subject: soc/intel/xeon_sp: Handle GPIO SMIs
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Patch Set 2:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/84301/comment/a93f6533_90fc1ecd?usp... :
PS2, Line 9: GPIO_SMI_STS
> Why do you need to handle GPIO_SMIs? Why are they enabled when there are no mainboard_smi_gpi_handle […]

Not sure if there are other codes to enable an SMI handler (and configure specific GPIOs in SMI modes). The changes in this patch seems not presenting a full background.

File src/soc/intel/xeon_sp/smihandler.c:

https://review.coreboot.org/c/coreboot/+/84301/comment/b6f7f82c_058e231f?usp... :
PS2, Line 92: #if CONFIG(CPU_INTEL_SOCKET_LGA3647_1)
The reason to use a socket type config selector is?