[coreboot-gerrit] Change in coreboot[master]: mb/ocp/tiogapass: Add UART init in bootblock

[Michael Niewöhner (Code Review)]

Attention is currently required from: David Hendricks.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39270 )

Change subject: mb/ocp/tiogapass: Add UART init in bootblock
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Patch Set 1:

(1 comment)

File src/mainboard/ocp/tiogapass/bootblock.c:

https://review.coreboot.org/c/coreboot/+/39270/comment/c3966795_e71341b1 
PS1, Line 24: 	/*
            : 	 * Set up decoding windows on PCH over PCR. The CPUs use two of AST2500 SIO ports,
            : 	 * one is connected to debug header and another is used as SOL.
            : 	 */
            : 	pcr_write32(PID_DMI, PCR_DMI_LPCIOD, (0 << 0) | (1 << 4));
            : 	pcr_write32(PID_DMI, PCR_DMI_LPCIOE, (1 << 0) | (1 << 1));
            : 	/* for unidentified reason lpc_io_setup_comm_a_b() doesn't work */
            : 	/* enable com1 and com2 and 0x3f8 and 0x2f8, and 0x2e */
            : 	pci_mmio_write_config32(PCH_DEV_LPC, 0x80,
            : 		(1<<28) | (1<<16) | (1<<17) | (0 << 0) | (1 << 4));
            : 
not needed anymore. just add select `SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE`