[coreboot-gerrit] Change in coreboot[master]: [WIP]mb/emulation/qemu-q35: Support PARALLEL_MP with SMM_ASEG

[Kyösti Mälkki (Code Review)]

Attention is currently required from: Arthur Heymans.
Hello Arthur Heymans,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/61494

to review the following change.

Change subject: [WIP]mb/emulation/qemu-q35: Support PARALLEL_MP with SMM_ASEG
......................................................................

[WIP]mb/emulation/qemu-q35: Support PARALLEL_MP with SMM_ASEG

Change-Id: I7db55aaabd16a6ef585c4802218790bf04650b13
Signed-off-by: Arthur Heymans 
Signed-off-by: Kyösti Mälkki 
---
M src/cpu/qemu-x86/Kconfig
M src/mainboard/emulation/qemu-i440fx/northbridge.c
M src/mainboard/emulation/qemu-q35/cpu.c
3 files changed, 34 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/61494/1

diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig
index 73aadfb..868009c 100644
--- a/src/cpu/qemu-x86/Kconfig
+++ b/src/cpu/qemu-x86/Kconfig
@@ -10,7 +10,6 @@

if CPU_QEMU_X86

-# coreboot i440fx does not support SMM
 choice
    prompt "AP init"
    default CPU_QEMU_X86_LAPIC_INIT
@@ -24,6 +23,7 @@

endchoice

+# coreboot i440fx does not support SMM
 choice
    prompt "SMM support"
    default CPU_QEMU_X86_ASEG_SMM
@@ -35,7 +35,6 @@

config CPU_QEMU_X86_ASEG_SMM
    bool "SMM in ASEG"
-	depends on CPU_QEMU_X86_LAPIC_INIT
    select SMM_ASEG

config CPU_QEMU_X86_TSEG_SMM
diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c
index 06aa83a..b55ace0 100644
--- a/src/mainboard/emulation/qemu-i440fx/northbridge.c
+++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c
@@ -247,7 +247,7 @@

void mp_init_cpus(struct bus *cpu_bus)
 {
-	const struct mp_ops *ops = CONFIG(SMM_TSEG) ? &mp_ops_with_smm : &mp_ops_no_smm;
+	const struct mp_ops *ops = CONFIG(NO_SMM) ? &mp_ops_no_smm : &mp_ops_with_smm;

/* TODO: Handle mp_init_with_smm failure? */
    mp_init_with_smm(cpu_bus, ops);
diff --git a/src/mainboard/emulation/qemu-q35/cpu.c b/src/mainboard/emulation/qemu-q35/cpu.c
index fb31fc5..1504f2d 100644
--- a/src/mainboard/emulation/qemu-q35/cpu.c
+++ b/src/mainboard/emulation/qemu-q35/cpu.c
@@ -1,5 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

+#define __SIMPLE_DEVICE__
+
 #include <console/console.h>
 #include <cpu/x86/mp.h>
 #include <stdint.h>
@@ -7,12 +9,41 @@
 #include <cpu/amd/amd64_save_state.h>
 #include <mainboard/emulation/qemu-i440fx/fw_cfg.h>

+#include <device/pci_ops.h>
+
+#include <mainboard/emulation/qemu-i440fx/memory.h>
+#include <mainboard/emulation/qemu-i440fx/fw_cfg.h>
+#include <cpu/intel/smm_reloc.h>
+#include <cpu/x86/smm.h>
+
+#include "q35.h"
+
+/* QEMU-specific register */
+#define EXT_TSEG_MBYTES 0x50
+#define SMRAMC 0x9d
+#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
+#define G_SMRAME (1 << 3)
+#define D_LCK (1 << 4)
+#define D_CLS (1 << 5)
+#define D_OPEN (1 << 6)
+#define ESMRAMC 0x9e
+#define T_EN (1 << 0)
+#define TSEG_SZ_MASK (3 << 1)
+#define H_SMRAME (1 << 7)
+
 static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
          size_t *smm_save_state_size)
 {
    printk(BIOS_DEBUG, "Setting up SMI for CPU\n");

-	smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize);
+	if (CONFIG(SMM_TSEG))
+		smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize);
+
+	if (CONFIG(SMM_ASEG)) {
+		pci_write_config8(PCI_DEV(0, 0, 0), SMRAMC, G_SMRAME | C_BASE_SEG | D_OPEN);
+		*perm_smbase = 0xa0000;
+		*perm_smsize = 0x10000;
+	}

/* FIXME: on X86_64 the save state size is smaller than the size of the SMM stub */
    *smm_save_state_size = sizeof(amd64_smm_state_save_area_t);