[coreboot-gerrit] Change in coreboot[master]: soc/intel/jasperlake: Add CdClock frequency config

[Nico Huber (Code Review)]

Attention is currently required from: Jamie Chen, Henry Sun, Paul Menzel, Tim Wawrzynczak, Ren Kuo, Simon Yang, Kane Chen, Patrick Rudolph.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60009 )

Change subject: soc/intel/jasperlake: Add CdClock frequency config
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Patch Set 25:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/60009/comment/268f5d59_7f938676 
PS17, Line 14:
> FSP related behavior already update to issue tracker b/206557434.

I don't know what that means exactly and have doubts that I'm authorized
to access this issue tracker (is it a 3rd party one? e.g. Google's?)

Generally, if downstream discussions happen behind closed doors, you
have to expect to repeat them upstream.