[coreboot-gerrit] [M] Change in coreboot[main]: soc/intel/lockdown: Allow locking down SPI and LPC in SMM

[Paul Menzel (Code Review)]

Attention is currently required from: Christian Walter, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jayvik Desai, Jeff Daly, Johnny Lin, Jonathan Zhang, Kapil Porwal, Lean Sheng Tan, Michał Żygowski, Nick Vaccaro, Patrick Rudolph, Pranava Y N, Subrata Banik, Tarun, Tim Chu, Vanessa Eusebio, Werner Zeh.

Paul Menzel has posted comments on this change by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/85278?usp=email )

Change subject: soc/intel/lockdown: Allow locking down SPI and LPC in SMM
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Patch Set 3:

(3 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/85278/comment/1bc100aa_c7700a9d?usp... :
PS3, Line 9: Heads payload uses APM_CNT_FINALIZE SMI to set and lock down the SPI
           : controller with PR0 flash protection for pre-Skylake platforms.
Could you elaborate, why Heads wants to do it and not let coreboot do it?

Reading this paragraph, I wondered, what about Skylake and later platforms?

File src/soc/intel/alderlake/finalize.c:

https://review.coreboot.org/c/coreboot/+/85278/comment/7d835f43_57e303f0?usp... :
PS3, Line 88: 	if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3())
Excuse my ignorance, why is `acpi_is_wakeup_s3()` added?

File src/soc/intel/common/pch/lockdown/Kconfig:

https://review.coreboot.org/c/coreboot/+/85278/comment/f2b8ddce_3c2c7753?usp... :
PS3, Line 21: heads
Heads