[coreboot-gerrit] Change in coreboot[master]: soc/amd/cezanne: Refactor ESPI Setup

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58114 )

Change subject: soc/amd/cezanne: Refactor ESPI Setup
......................................................................

soc/amd/cezanne: Refactor ESPI Setup

ESPI is setup in two different locations in bootblock depending on early
port80 routing configuration. Also ESPI is setup in PSP, if verified
boot starts before bootblock. Consolidate all the scenarios by
initializating ESPI at bootblock entry if verified boot starts after
bootblock.

BUG=None
TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm
reset and suspend/resume cycles for 50 iterations each.

Signed-off-by: Karthikeyan Ramasubramanian 
Change-Id: Icfeba17dae0a964c9ca73686e29c18d965589934
---
M src/soc/amd/cezanne/bootblock.c
M src/soc/amd/cezanne/early_fch.c
M src/soc/amd/cezanne/include/soc/southbridge.h
3 files changed, 7 insertions(+), 11 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/58114/1

diff --git a/src/soc/amd/cezanne/bootblock.c b/src/soc/amd/cezanne/bootblock.c
index fc1c5e7c..def0a78 100644
--- a/src/soc/amd/cezanne/bootblock.c
+++ b/src/soc/amd/cezanne/bootblock.c
@@ -92,12 +92,11 @@
    set_caching();
    write_resume_eip();
    enable_pci_mmconf();
-	/*
-	 * If NO_EARLY_BOOTBLOCK_POSTCODES is selected, we need to initialize port80h
-	 * routing as early as possible
-	 */
-	if (CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES))
-		configure_port80_routing_early();
+
+	/* If ESPI is setup in PSP Verstage, continue with that. Else setup ESPI to perform
+	   port80h routing as early as possible. */
+	if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK))
+		configure_espi();

/*
     * base_timestamp is raw tsc value. We need to divide by tsc_freq_mhz
diff --git a/src/soc/amd/cezanne/early_fch.c b/src/soc/amd/cezanne/early_fch.c
index bddcbee..834ca70 100644
--- a/src/soc/amd/cezanne/early_fch.c
+++ b/src/soc/amd/cezanne/early_fch.c
@@ -33,7 +33,7 @@
 }

/* Initialize port80h routing early if needed */
-void configure_port80_routing_early(void)
+void configure_espi(void)
 {
    if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) {
    	mb_set_up_early_espi();
@@ -78,7 +78,4 @@

if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING))
    	lpc_disable_spi_rom_sharing();
-
-	if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI) && !CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES))
-		espi_setup();
 }
diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h
index 31387b6..3dfad54 100644
--- a/src/soc/amd/cezanne/include/soc/southbridge.h
+++ b/src/soc/amd/cezanne/include/soc/southbridge.h
@@ -107,7 +107,7 @@
 #define   I2C_PAD_CTRL_SPARE0		BIT(17)
 #define   I2C_PAD_CTRL_SPARE1		BIT(18)

-void configure_port80_routing_early(void);
+void configure_espi(void);
 void fch_pre_init(void);
 void fch_early_init(void);
 void fch_init(void *chip_info);