Jamie Ryu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42788 )
Change subject: soc/intel/tgl: Add SkipCpuReplacementCheck to chip options ......................................................................
soc/intel/tgl: Add SkipCpuReplacementCheck to chip options
Add SkipCpuReplacementCheck to chip options to control UPD FSPM SkipCpuReplacementCheck from device tree. This UPD allows to skip CPU replacement check to avoid forced MRC traning with platforms with soldered down SoC.
TEST=boot and verified with volteer
Change-Id: Ic5782723ac3a204f2af657fac9944fb41fc03f4d Signed-off-by: Jamie Ryu jamie.m.ryu@intel.com --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params.c 2 files changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/42788/1
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index c72698f..432f857 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -365,6 +365,12 @@ /* External Vnn Voltage in mV */ int vnn_sx_voltage_mv; } ext_fivr_settings; + + /* + * Enable(0)/Disable(1) CPU Replacement check. + * Default 0. Setting this to 1 skips checking CPU replacement. + */ + uint8_t SkipCpuReplacementCheck; };
typedef struct soc_intel_tigerlake_config config_t; diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 1a46b7a..3eba69a 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -199,6 +199,9 @@
/* Command Pins Mirrored */ m_cfg->CmdMirror[0] = config->CmdMirror; + + /* Skip CPU replacement check */ + m_cfg->SkipCpuReplacementCheck = config->SkipCpuReplacementCheck; }
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)