Jason Glenesk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45340 )
Change subject: soc/amd/picasso: Generate ACPI pstate and cstate objects in cb ......................................................................
Patch Set 10:
(6 comments)
https://review.coreboot.org/c/coreboot/+/45340/5/src/include/cpu/amd/msr.h File src/include/cpu/amd/msr.h:
https://review.coreboot.org/c/coreboot/+/45340/5/src/include/cpu/amd/msr.h@6... PS5, Line 60: 0x30
There's some relevant discussion in https://review.coreboot. […]
Changing to 0x3e as you recommended in the other review. May have to come back and implement the single function to use across the board in another review.
https://review.coreboot.org/c/coreboot/+/45340/5/src/soc/amd/picasso/acpi.c File src/soc/amd/picasso/acpi.c:
https://review.coreboot.org/c/coreboot/+/45340/5/src/soc/amd/picasso/acpi.c@... PS5, Line 343: 3
PPR says that we support up to 3 Cstates, however it only defines values for C1 and C2 and agesa doe […]
Done
https://review.coreboot.org/c/coreboot/+/45340/5/src/soc/amd/picasso/acpi.c@... PS5, Line 362: 0x414
Doh! I meant to replace this with the right value, vs what i took from the agesa tables. […]
Done
https://review.coreboot.org/c/coreboot/+/45340/5/src/soc/amd/picasso/acpi.c@... PS5, Line 383: if (cpu == 0) {
There would be no harm in making this look like Intel vs. […]
Done
https://review.coreboot.org/c/coreboot/+/45340/7/src/soc/amd/picasso/acpi.c File src/soc/amd/picasso/acpi.c:
https://review.coreboot.org/c/coreboot/+/45340/7/src/soc/amd/picasso/acpi.c@... PS7, Line 170: void write_pct_object(void)
Good point. Will make these static.
Done
https://review.coreboot.org/c/coreboot/+/45340/7/src/soc/amd/picasso/acpi.c@... PS7, Line 310: acpigen_write_package(0x08);
That's fair. […]
Done