Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74236 )
Change subject: mb/google/sarien: Add method to set GPIOs in romstage ......................................................................
mb/google/sarien: Add method to set GPIOs in romstage
Add method variant_romstage_gpio_table() with empty implementation to be used in a subsequent commit for touchscreen power sequencing. Call method in romstage to program any GPIOs that may need to be set.
TEST=tested with rest of patch train
Change-Id: I11b72a10a4a105385fbcf1d795c020708a7a90d9 Signed-off-by: Matt DeVillier matt.devillier@gmail.com --- M src/mainboard/google/sarien/romstage.c M src/mainboard/google/sarien/variants/arcada/gpio.c M src/mainboard/google/sarien/variants/arcada/include/variant/gpio.h M src/mainboard/google/sarien/variants/sarien/gpio.c M src/mainboard/google/sarien/variants/sarien/include/variant/gpio.h 5 files changed, 37 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/74236/1
diff --git a/src/mainboard/google/sarien/romstage.c b/src/mainboard/google/sarien/romstage.c index bc0a799..8045112 100644 --- a/src/mainboard/google/sarien/romstage.c +++ b/src/mainboard/google/sarien/romstage.c @@ -3,6 +3,7 @@ #include <ec/google/wilco/romstage.h> #include <soc/cnl_memcfg_init.h> #include <soc/romstage.h> +#include <variant/gpio.h>
static const struct cnl_mb_cfg memcfg = { /* Access memory info through SMBUS. */ @@ -44,7 +45,13 @@
void mainboard_memory_init_params(FSPM_UPD *memupd) { + const struct pad_config *pads; + size_t pads_num; + wilco_ec_romstage_init();
cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); + + pads = variant_romstage_gpio_table(&pads_num); + gpio_configure_pads(pads, pads_num); } diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c index fbaeb39..63df675 100644 --- a/src/mainboard/google/sarien/variants/arcada/gpio.c +++ b/src/mainboard/google/sarien/variants/arcada/gpio.c @@ -254,6 +254,12 @@ return early_gpio_table; }
+const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} + static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(GPP_E8, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPP_E15, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/gpio.h b/src/mainboard/google/sarien/variants/arcada/include/variant/gpio.h index f56059c..0472f60 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/gpio.h +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/gpio.h @@ -14,5 +14,6 @@
const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); +const struct pad_config *variant_romstage_gpio_table(size_t *num);
#endif diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c index 7f226e4..f9797d3 100644 --- a/src/mainboard/google/sarien/variants/sarien/gpio.c +++ b/src/mainboard/google/sarien/variants/sarien/gpio.c @@ -242,6 +242,12 @@ return early_gpio_table; }
+const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} + static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(GPP_E8, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPP_E15, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/gpio.h b/src/mainboard/google/sarien/variants/sarien/include/variant/gpio.h index f56059c..0472f60 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/gpio.h +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/gpio.h @@ -14,5 +14,6 @@
const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); +const struct pad_config *variant_romstage_gpio_table(size_t *num);
#endif