Alicja Michalska has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85641?usp=email )
Change subject: mb/erying/tgl: Cleanup the code ......................................................................
mb/erying/tgl: Cleanup the code
This patch cleans the code by: - Removing CMOS layout (I need to sit down and write layout) - Moving SuperIO configuration to bootblock to make devtree cleaner - Adding sane value for PCI-E ReBAR
Additionally, it fixes responsiveness of the power button (it was flaky before), and S3 state *almost* works now (RAM content doesn't get lost, but for some reason Memory Controller wipes MRC Cache on resume from S3).
Change-Id: I9e395220025fc13e0589472e4732ea1495668554 Signed-off-by: Alicja Michalska ahplka19@gmail.com --- M src/mainboard/erying/tgl/Kconfig M src/mainboard/erying/tgl/bootblock.c D src/mainboard/erying/tgl/cmos.layout M src/mainboard/erying/tgl/devicetree.cb M src/mainboard/erying/tgl/dsdt.asl 5 files changed, 26 insertions(+), 62 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/85641/1
diff --git a/src/mainboard/erying/tgl/Kconfig b/src/mainboard/erying/tgl/Kconfig index 01e5dd98..f32fa82 100644 --- a/src/mainboard/erying/tgl/Kconfig +++ b/src/mainboard/erying/tgl/Kconfig @@ -13,10 +13,9 @@ select HAVE_ACPI_TABLES select SUPERIO_ITE_IT8613E select DRIVERS_UART_8250IO - select HAVE_CMOS_DEFAULT - select HAVE_OPTION_TABLE select HAVE_INTEL_PTT select CRB_TPM + select PCIEXP_SUPPORT_RESIZABLE_BARS
config MAINBOARD_SMBIOS_PRODUCT_NAME default "POLESTAR G613 Pro" @@ -30,6 +29,10 @@ config CBFS_SIZE default 0xA00000
+config PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS + int + default 42 + config USE_PM_ACPI_TIMER default n
diff --git a/src/mainboard/erying/tgl/bootblock.c b/src/mainboard/erying/tgl/bootblock.c index 15be8ce..c886905 100644 --- a/src/mainboard/erying/tgl/bootblock.c +++ b/src/mainboard/erying/tgl/bootblock.c @@ -3,14 +3,25 @@ #include <bootblock_common.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8613e/it8613e.h> -#include <gpio.h>
#define GPIO_DEV PNP_DEV(0x2e, IT8613E_GPIO) #define UART_DEV PNP_DEV(0x2e, IT8613E_SP1)
void bootblock_mainboard_early_init(void) { - ite_reg_write(GPIO_DEV, 0x29, 0xc1); /* 3VSB - RAM loses power in S3 anyway */ - ite_reg_write(GPIO_DEV, 0x2c, 0x41); /* disable k8 power seq */ + ite_reg_write(GPIO_DEV, 0x22, 0x0c); + ite_reg_write(GPIO_DEV, 0x26, 0xf3); + ite_reg_write(GPIO_DEV, 0x29, 0x01); + ite_reg_write(GPIO_DEV, 0x2c, 0x41); + ite_reg_write(GPIO_DEV, 0x2d, 0x02); + ite_reg_write(GPIO_DEV, 0x71, 0x01); + ite_reg_write(GPIO_DEV, 0xbc, 0xc0); + ite_reg_write(GPIO_DEV, 0xbd, 0x03); + ite_reg_write(GPIO_DEV, 0xc1, 0x02); + ite_reg_write(GPIO_DEV, 0xc8, 0x00); + ite_reg_write(GPIO_DEV, 0xc9, 0x02); + ite_reg_write(GPIO_DEV, 0xda, 0xb0); + ite_reg_write(GPIO_DEV, 0xdb, 0x44); + ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/erying/tgl/cmos.layout b/src/mainboard/erying/tgl/cmos.layout deleted file mode 100644 index a53c3f4..0000000 --- a/src/mainboard/erying/tgl/cmos.layout +++ /dev/null @@ -1,39 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -entries - -0 384 r 0 reserved_memory - -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter - -# RTC_CLK_ALTCENTURY -400 8 r 0 century - -412 4 e 6 debug_level -416 1 e 2 me_state -417 3 h 0 me_state_counter -984 16 h 0 check_sum - -enumerations - -2 0 Enable -2 1 Disable - -4 0 Fallback -4 1 Normal - -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew - -checksums - -checksum 408 983 984 diff --git a/src/mainboard/erying/tgl/devicetree.cb b/src/mainboard/erying/tgl/devicetree.cb index 55744c4..57ac733 100644 --- a/src/mainboard/erying/tgl/devicetree.cb +++ b/src/mainboard/erying/tgl/devicetree.cb @@ -17,10 +17,9 @@ register "eist_enable" = "1" register "enable_c6dram" = "1"
+ register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN" register "deep_s3_enable_ac" = "1" - register "deep_s3_enable_dc" = "1" register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1"
# PME routing register "pmc_gpe0_dw0" = "PMC_GPP_R" @@ -134,11 +133,11 @@
device ref pch_espi on chip superio/ite/it8613e - device pnp 2e.0 off end + device pnp 2e.0 off end # FDC device pnp 2e.1 on # COM 1 io 0x60 = 0x3f8 - irq 0x70 = 4 - irq 0xf0 = 1 + irq 0x70 = 0x04 + irq 0xf0 = 0x01 end
device pnp 2e.4 on # Environment Controller @@ -172,22 +171,12 @@ register "FAN3.smart.slope" = "24" end
- device pnp 2e.5 off end - device pnp 2e.6 off end + device pnp 2e.5 off end # Keyboard + device pnp 2e.6 off end # Mouse
device pnp 2e.7 on # GPIO - irq 0x2d = 0x02 io 0x60 = 0xa10 io 0x62 = 0xa00 - irq 0x70 = 0x00 - irq 0x71 = 0x01 - irq 0xbc = 0xc0 - irq 0xbd = 0x03 - irq 0xc1 = 0x02 - irq 0xc8 = 0x00 - irq 0xc9 = 0x02 - irq 0xda = 0xb0 - irq 0xdb = 0x44 end device pnp 2e.a off end # CIR end diff --git a/src/mainboard/erying/tgl/dsdt.asl b/src/mainboard/erying/tgl/dsdt.asl index 61898a9..e10b61c 100644 --- a/src/mainboard/erying/tgl/dsdt.asl +++ b/src/mainboard/erying/tgl/dsdt.asl @@ -21,6 +21,6 @@ #include <soc/intel/tigerlake/acpi/southbridge.asl> #include <soc/intel/tigerlake/acpi/tcss.asl> } - + #include <southbridge/intel/common/acpi/sleepstates.asl> }