build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44717 )
Change subject: soc/mediatek/mt8192: Do write leveling training ......................................................................
Patch Set 1:
(18 comments)
https://review.coreboot.org/c/coreboot/+/44717/1/src/soc/mediatek/mt8192/dra... File src/soc/mediatek/mt8192/dramc_pi_basic_api.c:
https://review.coreboot.org/c/coreboot/+/44717/1/src/soc/mediatek/mt8192/dra... PS1, Line 4099: static void shift_dq_oen_ui(const struct ddr_cali* cali, u8 rk) "foo* bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/44717/1/src/soc/mediatek/mt8192/dra... PS1, Line 4106: {&ch[chn].ao.shu_rk[rk].shurk_selph_dq2, 20}}; space required after that close brace '}'
https://review.coreboot.org/c/coreboot/+/44717/1/src/soc/mediatek/mt8192/dra... PS1, Line 4110: {&ch[chn].ao.shu_rk[rk].shurk_selph_dq0, 20}}; space required after that close brace '}'
https://review.coreboot.org/c/coreboot/+/44717/1/src/soc/mediatek/mt8192/dra... PS1, Line 4116: static void shift_dqs_ui(const struct ddr_cali* cali, s8 shift_ui, u8 byte) "foo* bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/44717/1/src/soc/mediatek/mt8192/dra... PS1, Line 4133: {&ch[chn].ao.shu_selph_dqs1, 4}}; space required after that close brace '}'
https://review.coreboot.org/c/coreboot/+/44717/1/src/soc/mediatek/mt8192/dra... PS1, Line 4135: {&ch[chn].ao.shu_selph_dqs0, 4}}; space required after that close brace '}'
https://review.coreboot.org/c/coreboot/+/44717/1/src/soc/mediatek/mt8192/dra... PS1, Line 4140: static void shift_dqs_oen_ui(const struct ddr_cali* cali, s8 shift_ui, u8 byte) "foo* bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/44717/1/src/soc/mediatek/mt8192/dra... PS1, Line 4157: {&ch[chn].ao.shu_selph_dqs1, 20}}; space required after that close brace '}'
https://review.coreboot.org/c/coreboot/+/44717/1/src/soc/mediatek/mt8192/dra... PS1, Line 4159: {&ch[chn].ao.shu_selph_dqs0, 20}}; space required after that close brace '}'
https://review.coreboot.org/c/coreboot/+/44717/1/src/soc/mediatek/mt8192/dra... PS1, Line 4164: static void shift_dq_ui_all_rk(const struct ddr_cali* cali) "foo* bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/44717/1/src/soc/mediatek/mt8192/dra... PS1, Line 4171: static void shift_dq_oen_ui_all_rk(const struct ddr_cali* cali) "foo* bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/44717/1/src/soc/mediatek/mt8192/dra... PS1, Line 4177: static void shift_dqs_wck_ui(const struct ddr_cali* cali, s8 shift_ui, u8 byte) "foo* bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/44717/1/src/soc/mediatek/mt8192/dra... PS1, Line 4183: static void write_leveling_move_dqs_instead_of_clk(const struct ddr_cali* cali) "foo* bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/44717/1/src/soc/mediatek/mt8192/dra... PS1, Line 4198: static void set_dram_mr_write_leveling(const struct ddr_cali* cali, bool state) "foo* bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/44717/1/src/soc/mediatek/mt8192/dra... PS1, Line 4205: if (state) suspect code indent for conditional statements (8, 12)
https://review.coreboot.org/c/coreboot/+/44717/1/src/soc/mediatek/mt8192/dra... PS1, Line 4207: else suspect code indent for conditional statements (8, 12)
https://review.coreboot.org/c/coreboot/+/44717/1/src/soc/mediatek/mt8192/dra... PS1, Line 4213: void dramc_write_leveling(const struct ddr_cali* cali, u8 wl_dqs_final_delay[2][2]) "foo* bar" should be "foo *bar"
https://review.coreboot.org/c/coreboot/+/44717/1/src/soc/mediatek/mt8192/dra... PS1, Line 4270: shift_ui = (wl_dqs_final_delay[rank][byte] / pi_bound) * (pi_bound / 32); line over 96 characters