[coreboot-gerrit] [S] Change in coreboot[main]: [TEST]soc/intel/meteorlake: Update TBT PCIe MPC offset for QS

[Ravishankar Sarawadi (Code Review)]

Ravishankar Sarawadi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78163?usp=email )

Change subject: [TEST]soc/intel/meteorlake: Update TBT PCIe MPC offset for QS
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[TEST]soc/intel/meteorlake: Update TBT PCIe MPC offset for QS

Within TBT PCIe, MPC register offsets have been updated for
production silicon. Update ASL with new offsets.

TEST= Check TBT PCIe Tunnnel creation and device enumration.
Change-Id: I0497f7108ef5046c2694aece232263582514a0c5
Signed-off-by: Ravi Sarawadi 
---
M src/soc/intel/meteorlake/acpi/tcss_pcierp.asl
1 file changed, 16 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/78163/1

diff --git a/src/soc/intel/meteorlake/acpi/tcss_pcierp.asl b/src/soc/intel/meteorlake/acpi/tcss_pcierp.asl
index 6dbde46..658576b 100644
--- a/src/soc/intel/meteorlake/acpi/tcss_pcierp.asl
+++ b/src/soc/intel/meteorlake/acpi/tcss_pcierp.asl
@@ -25,14 +25,25 @@
    PSPX, 1,       /* 16,  PME Status */
    Offset(0xA4),
    D3HT, 2,       /* Power State */
+#if CONFIG(SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON)
    Offset(0xD8),  /* 0xD8, MPC - Miscellaneous Port Configuration Register */
+        , 30,
+        HPEX, 1,       /* 30,  Hot Plug SCI Enable */
+        PMEX, 1,       /* 31,  Power Management SCI Enable */
+        Offset(0xE2),  /* 0xE2, RPPGEN - Root Port Power Gating Enable */
+        , 2,
+        L23E, 1,       /* 2,   L23_Rdy Entry Request (L23ER) */
+        L23R, 1,       /* 3,   L23_Rdy to Detect Transition (L23R2DT) */
+#else
+	Offset(0xBA8),  /* 0xBA8, MPC - Miscellaneous Port Configuration Register */
    , 30,
    HPEX, 1,       /* 30,  Hot Plug SCI Enable */
    PMEX, 1,       /* 31,  Power Management SCI Enable */
-	Offset(0xE2),  /* 0xE2, RPPGEN - Root Port Power Gating Enable */
+	Offset(0xBB2),  /* 0xBB2, RPPGEN - Root Port Power Gating Enable */
    , 2,
    L23E, 1,       /* 2,   L23_Rdy Entry Request (L23ER) */
    L23R, 1,       /* 3,   L23_Rdy to Detect Transition (L23R2DT) */
+#endif
    Offset(0x420), /* 0x420, PCIEPMECTL (PCIe PM Extension Control) */
    , 30,
    DPGE, 1,       /* PCIEPMECTL[30]: Disabled, Detect and L23_Rdy State PHY Lane */
@@ -45,7 +56,11 @@

Field (PXCS, AnyAcc, NoLock, WriteAsZeros)
 {
+#if CONFIG(SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON)
    Offset(0xDC),  /* 0xDC, SMSCS - SMI/SCI Status Register */
+#else
+	Offset(0xBAC),  /* 0xBAC, SMSCS - SMI/SCI Status Register */
+#endif
    , 30,
    HPSX, 1,       /* 30,  Hot Plug SCI Status */
    PMSX, 1        /* 31,  Power Management SCI Status */