[coreboot-gerrit] [M] Change in coreboot[main]: soc/intel/xeon_sp: Add acpigen_write_pci_root_port

[Patrick Rudolph (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu.

Patrick Rudolph has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/82252?usp=email )

Change subject: soc/intel/xeon_sp: Add acpigen_write_pci_root_port
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Patch Set 6:

(1 comment)

File src/soc/intel/xeon_sp/acpi.c:

https://review.coreboot.org/c/coreboot/+/82252/comment/037ec8c2_6d0eba3c?usp... :
PS6, Line 192: PCI_SECONDARY_BUS
are there root ports that do not act as a bridge and thus have PCI_SECONDARY_BUS==0?