[coreboot-gerrit] [XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock

[Saurabh Mishra (Code Review)]

Attention is currently required from: Ashish Kumar Mishra, Dinesh Gehlot, Elyes Haouas, Eran Mitrani, Felix Singer, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Subrata Banik, Tarun.

Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83354?usp=email )

Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
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Patch Set 36:

(1 comment)

File src/soc/intel/pantherlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/83354/comment/711c3508_d298c4b6?usp... :
PS30, Line 141: 0xfe02c000
> > why would FSP even bother to initialise the UART when we are setting UPD to PchSerialIoSkipInit to […]

we don't use FSP-T hence, ideally this is not applicable to us.
> Hi Subrata, yes, so to align the LPSS UART Base Addr b/w FSP and Coreboot, it would be good to have a UPD in FSP-M/S. We are working with FSP Team.