[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: set LT_LOCK_MEMORY at end of POST

[Michael Niewöhner (Code Review)]

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36356 )

Change subject: soc/intel/cannonlake: set LT_LOCK_MEMORY at end of POST
......................................................................

Patch Set 2:
> Patch Set 2:
> > Patch Set 2: Code-Review+1
> >
> > Actually, same as on ICL. CNL doesn't have `SkipMpInit`, it seems to be
> > somewhere between FSP 2.0 and 2.1.
> >
> > Subrata, do you know what the lack of SkipMpInit for CNL implies?
>
> SkipMpInit wasn't removed but moved from FSP-S to FSP-M. I checked the FSP binary. It does only set the lock if SkipMpInit=0.

I got confirmation from Nate that the FSP-M SkipMpInit does "more or less" the same, as it did before. I should get my CML device by end of the week, so I can do a test on hardware