[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/basecode: Implement CSE update flow

[Sridhar Siricilla (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Sridhar Siricilla, Rizwan Qureshi, Subrata Banik, Balaji Manigandan, Aamir Bohra, Patrick Rudolph, V Sowmya, Andrey Petrov, Jamie Ryu, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35403

to look at the new patch set (#70).

Change subject: soc/intel/common/basecode: Implement CSE update flow
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soc/intel/common/basecode: Implement CSE update flow

This is the core patch that implement CSE FW update flow.

To enable the FW update flow the following are required:

* Descriptor change to accommodate a larger CSME region
    The CSME size is 4.1MB.

* FMAP changes to accommodate ME update binary in RW CBFSes & larger
  CSE binary.
    Due to the increased CSME binary size and to accommodate the extra
    CSME RW binaries (which are ~2.5 MB) in RW CBFSes, the board FMAP has
    to be modified.

* The new CSE binary with new partitions and respective RW area binaries.

The following changes have been done in this patch:

* Implement Update flow
  Get the partition info containing version of ME RW using
    GET_BOOT_PARTITION_INFO HECI command
  Get the me_rw.version from the currently selected RW slot.
  If the version from the above 2 locations don't match start the update
   - Set the CSE's next boot partition to RO using SET_BOOT_PARTITION
     HECI command.
   - Send global reset command to reset only the CSME
   - Wait for CSME to enter SOFT_TEMP_DISABLE operation mode
     (indicated by HFSTS1 register bit 19:16)
   - Enable HMRFPO (Host ME Region Flash Protection Override) using the
     HMRFPO_ENABLE HECI command
   - Erase and Copy the CBFS ME RW to ME RW partition
   - Set the CSE's next boot partition to RW using
     SET_BOOT_PARTITION HECI command
   - Trigger global reset
   The system should boot with the Updated ME

Verified basic update flows on Cometlake RVP and hatch.

BUG=b:111330995

Change-Id: I12f6bba3324069d65edabaccd234006b0840e700
Signed-off-by: Rizwan Qureshi 
Signed-off-by: Sridhar Siricilla 
Signed-off-by: V Sowmya 
---
A Documentation/soc/intel/cse_fw_update/Layout_after.svg
A Documentation/soc/intel/cse_fw_update/Layout_before.svg
A Documentation/soc/intel/cse_fw_update/cse_fw_update.md
M Documentation/soc/intel/index.md
M src/soc/intel/cannonlake/me.c
M src/soc/intel/common/block/cse/Kconfig
M src/soc/intel/common/block/cse/custom_bp.c
M src/soc/intel/common/block/include/intelblocks/cse.h
8 files changed, 747 insertions(+), 14 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/35403/70