Attention is currently required from: Hung-Te Lin, Kiwi Liu, Mengqi Zhang, Paul Menzel, Yidi Lin.
Yu-Ping Wu has posted comments on this change by Kiwi Liu. ( https://review.coreboot.org/c/coreboot/+/84298?usp=email )
Change subject: soc/mediatek/common: Reduce eMMC clock frequency to 400kHz
......................................................................
Patch Set 14:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84298/comment/b30fa093_19012e22?usp... :
PS14, Line 13: he frequency
: division value to 125
and get the division value 125.
I don't think the origin code will give us the 125 value due to the division rounding error.
```
div = DIV_ROUND_UP(hclk, clock * 4)
= DIV_ROUND_UP(50M / (400K * 4))
= DIV_ROUND_UP(31.25)
= 32
```
So the division value will be `div` * 4 = 128.
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