Joey Peng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56754 )
Change subject: mb/google/brya/variants/taeko: Configure GPIOs according to schematics ......................................................................
mb/google/brya/variants/taeko: Configure GPIOs according to schematics
Update initial gpio configuration for taeko
BUG=b:195252436
TEST=FW_NAME=taeko emerge-brya coreboot
Change-Id: Ida1edbf874c93f6efac45c276920ead9311ac6f2 --- A src/mainboard/google/brya/variants/taeko/Makefile.inc A src/mainboard/google/brya/variants/taeko/gpio.c 2 files changed, 221 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/56754/1
diff --git a/src/mainboard/google/brya/variants/taeko/Makefile.inc b/src/mainboard/google/brya/variants/taeko/Makefile.inc new file mode 100644 index 0000000..8914639 --- /dev/null +++ b/src/mainboard/google/brya/variants/taeko/Makefile.inc @@ -0,0 +1,2 @@ +bootblock-y += gpio.c +ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/taeko/gpio.c b/src/mainboard/google/brya/variants/taeko/gpio.c new file mode 100644 index 0000000..9c495d4 --- /dev/null +++ b/src/mainboard/google/brya/variants/taeko/gpio.c @@ -0,0 +1,219 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> +#include <soc/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_override_table[] = { + /* A6 : ESPI_ALERT1# ==> NC */ + PAD_NC(GPP_A6, NONE), + /* A7 : SRCCLK_OE7# ==> NC */ + PAD_NC(GPP_A7, NONE), + /* A8 : SRCCLKREQ7# ==> NC */ + PAD_NC(GPP_A8, NONE), + /* A9 : ESPI_CLK ==> ESPI_CLK */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + /* A10 : ESPI_RESET# ==> ESPI_PCH_RST_EC_L */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + /* A11 : PMC_I2C_SDA ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_A11, UP_20K, 1, DEEP), + /* A12 : SATAXPCIE1 ==> NC */ + PAD_NC(GPP_A12, NONE), + /* A14 : USB_OC1# ==> NC */ + PAD_NC(GPP_A14, NONE), + /* A15 : USB_OC2# ==> NC */ + PAD_NC(GPP_A15, NONE), + /* A17 : DISP_MISCC ==> EN_FCAM_PWR */ + PAD_CFG_GPO(GPP_A17, UP_20K, 1, DEEP), + /* A18 : DDSP_HPDB ==> NC */ + PAD_NC(GPP_A18, NONE), + /* A19 : DDSP_HPD1 ==> NC */ + PAD_NC(GPP_A19, NONE), + /* A20 : DDSP_HPD2 ==> NC */ + PAD_NC(GPP_A20, NONE), + /* A21 : DDPC_CTRCLK ==> NC */ + PAD_NC(GPP_A21, NONE), + /* A22 : DDPC_CTRLDATA ==> NC */ + PAD_NC(GPP_A22, NONE), + /* A23 : ESPI_CS1# ==> AUD_HP_INT_L */ + PAD_CFG_GPI_INT(GPP_A23, UP_20K NONE, PLTRST, EDGE_BOTH), + + /* B2 : VRALERT# ==> NC */ + PAD_NC(GPP_B2, NONE), + /* B3 : PROC_GP2 ==> NC */ + PAD_NC(GPP_B3, NONE), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, UP_20K, 1, DEEP), + /* B15 : TIME_SYNC0 ==> NC */ + PAD_NC(GPP_B15, NONE), + + /* C0 : SMBCLK ==> EN_PP3300_TCHSCR */ + PAD_CFG_GPO(GPP_C0, UP_20K, 1, DEEP), + /* C1 : SMBDATA ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C1, UP_20K, 0, DEEP), + /* C3 : SML0CLK ==> NC */ + PAD_NC(GPP_C3, NONE), + /* C4 : SML0DATA ==> NC */ + PAD_NC(GPP_C4, NONE), + /* C6 : SML1CLK ==> NC */ + PAD_NC(GPP_C6, NONE), + /* C7 : SML1DATA ==> USI_INT */ + PAD_CFG_GPI_APIC(GPP_C7, NONE, PLTRST, LEVEL, NONE), + + /* D2 : ISH_GP2 ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_D2, UP_20K, 1, DEEP), + /* D3 : ISH_GP3 ==> NC */ + PAD_NC(GPP_D3, NONE), + /* D4 : IMGCLKOUT0 ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_D4, UP_20K, 1, DEEP), + /* D5 : SRCCLKREQ0# ==> NC */ + PAD_NC(GPP_D5, NONE), + /* D9 : ISH_SPI_CS# ==> NC */ + PAD_NC(GPP_D9, NONE), + /* D10 : ISH_SPI_CLK ==> NC */ + PAD_NC(GPP_D10, NONE), + /* D13 : ISH_UART0_RXD ==> NC */ + PAD_NC(GPP_D13, NONE), + /* D14 : ISH_UART0_TXD ==> NC */ + PAD_NC(GPP_D14, NONE), + /* D15 : ISH_UART0_RTS# ==> NC */ + PAD_NC(GPP_D15, NONE), + /* D16 : ISH_UART0_CTS# ==> NC */ + PAD_NC(GPP_D16, NONE), + /* D17 : UART1_RXD ==> NC */ + PAD_NC(GPP_D17, NONE), + /* D18 : UART1_TXD ==> SD_PE_RST_L */ + PAD_CFG_GPO(GPP_D18, UP_20K, 1, DEEP), + + /* E0 : SATAXPCIE0 ==> NC */ + PAD_NC(GPP_E0, NONE), + /* E3 : PROC_GP0 ==> HPS_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E3, UP_20K, NONE, PLTRST, EDGE_BOTH), + /* E4 : SATA_DEVSLP0 ==> NC */ + PAD_NC(GPP_E4, NONE), + /* E5 : SATA_DEVSLP1 ==> NC */ + PAD_NC(GPP_E5, NONE), + /* E6 : THC0_SPI1_RST# ==> NC */ + PAD_NC(GPP_E6, NONE), + /* E7 : PROC_GP1 ==> EN_HPS_PWR */ + PAD_CFG_GPO(GPP_E7, UP_20K, 1, DEEP), + /* E8 : SLP_DRAM# ==> WIFI_DISABLE_L */ + PAD_CFG_GPO(GPP_E8, UP_20K, 1, DEEP), + /* E10 : THC0_SPI1_CS# ==> NC */ + PAD_NC(GPP_E10, NONE), + /* E16 : RSVD_TP ==> NC */ + PAD_NC(GPP_E16, NONE), + /* E17 : THC0_SPI1_INT# ==> NC */ + PAD_NC(GPP_E17, NONE), + /* E18 : DDP1_CTRLCLK ==> NC */ + PAD_NC(GPP_E18, NONE), + /* E19 : DDP1_CTRLDATA ==> NC */ + PAD_NC(GPP_E19, NONE), + /* E20 : DDP2_CTRLCLK ==> NC */ + PAD_NC(GPP_E20, NONE), + /* E21 : DDP2_CTRLDATA ==> NC */ + PAD_NC(GPP_E21, NONE), + + /* F6 : CNV_PA_BLANKING ==> NC */ + PAD_NC(GPP_F6, NONE), + /* F9 : BOOTMPC ==> SLP_S0_GATE_R */ + PAD_CFG_GPO(GPP_F9, 0, PLTRST), + /* F15 : GSXSRESET# ==> FPMCU_INT_L */ + PAD_CFG_GPI_IRQ_WAKE(GPP_F15, UP_20K NONE, DEEP, LEVEL, INVERT), + /* F19 : SRCCLKREQ6# ==> NC */ + PAD_NC(GPP_F19, NONE), + /* F20 : EXT_PWR_GATE# ==> NC */ + PAD_NC(GPP_F20, NONE), + /* F21 : EXT_PWR_GATE2# ==> NC */ + PAD_NC(GPP_F21, NONE), + /* F22 : VNN_CTRL ==> VNN_CTRL */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* F23 : BP105_CTRL ==> PP1050_CTRL */ + PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), + + /* H8 : I2C4_SDA ==> NC */ + PAD_NC(GPP_H8, NONE), + /* H9 : I2C4_SCL ==> NC */ + PAD_NC(GPP_H9, NONE), + /* H13 : I2C7_SCL ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_H13, UP_20K, 1, DEEP), + /* H15 : DDPB_CTRLCLK ==> NC */ + PAD_NC(GPP_H15, NONE), + /* H17 : DDPB_CTRLDATA ==> NC */ + PAD_NC(GPP_H17, NONE), + /* H19 : SRCCLKREQ4# ==> NC */ + PAD_NC(GPP_H19, NONE), + /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H20, UP_20K, 1, DEEP), + /* H21 : IMGCLKOUT2 ==> NC */ + PAD_NC(GPP_H21, NONE), + /* H22 : IMGCLKOUT3 ==> NC */ + PAD_NC(GPP_H22, NONE), + /* H23 : SRCCLKREQ5# ==> NC */ + PAD_NC(GPP_H23, NONE), + + /* R7 : I2S2_RXD ==> NC */ + PAD_NC(GPP_R7, NONE), + + /* S0 : SNDW0_CLK ==> NC */ + PAD_NC(GPP_S0, NONE), + /* S1 : SNDW0_DATA ==> NC */ + PAD_NC(GPP_S1, NONE), + /* S4 : SNDW2_CLK ==> NC */ + PAD_NC(GPP_S4, NONE), + /* S5 : SNDW2_DATA ==> NC */ + PAD_NC(GPP_S5, NONE), + /* S6 : SNDW3_CLK ==> NC */ + PAD_NC(GPP_S6, NONE), + /* S7 : SNDW3_DATA ==> NC */ + PAD_NC(GPP_S7, NONE), + + /* GPD11: LANPHYC ==> WWAN_CONFIG1 */ + PAD_NC(GPD11, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), + /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + /* + * D1 : ISH_GP1 ==> FP_RST_ODL + * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. + * To ensure proper power sequencing for the FPMCU device, reset signal is driven low + * early on in bootblock, followed by enabling of power. Reset signal is deasserted + * later on in ramstage. Since reset signal is asserted in bootblock, it results in + * FPMCU not working after a S3 resume. This is a known issue. + */ + PAD_CFG_GPO(GPP_D1, 0, DEEP), + /* D2 : ISH_GP2 ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_D2, UP_20K, 1, DEEP), + /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_E13, NONE, DEEP), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* H13 : I2C7_SCL ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_H13, UP_20K, 1, DEEP), +}; + +const struct pad_config *__weak variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *__weak variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} \ No newline at end of file