[coreboot-gerrit] Patch set updated for coreboot: c7ce370 Rename SANDYBRIDGE_BCLK to NEHALEM_BCLK in 2065x.

[Vladimir Serbinenko]

Vladimir Serbinenko ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4046

-gerrit

commit c7ce37018e6136265abc7bd301b95e2a7688a297
Author: Vladimir Serbinenko 
Date:   Tue Nov 12 23:32:52 2013 +0100

Rename SANDYBRIDGE_BCLK to NEHALEM_BCLK in 2065x.

2065x is with nehalem and not sandybridge.

I don't care much eitherway but it clears some confusion.

Change-Id: Ib2b8e570b830a12ed8d0d313ee4eb56755796d4b
    Signed-off-by: Vladimir Serbinenko 
---
 src/cpu/intel/model_2065x/acpi.c             | 4 ++--
 src/cpu/intel/model_2065x/model_2065x.h      | 4 ++--
 src/cpu/intel/model_2065x/model_2065x_init.c | 2 +-
 src/cpu/intel/model_2065x/tsc_freq.c         | 2 +-
 4 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/cpu/intel/model_2065x/acpi.c b/src/cpu/intel/model_2065x/acpi.c
index 8483812..fa0dc95 100644
--- a/src/cpu/intel/model_2065x/acpi.c
+++ b/src/cpu/intel/model_2065x/acpi.c
@@ -237,7 +237,7 @@ static int generate_P_state_entries(int core, int cores_per_package)
    	/* Max Non-Turbo Ratio */
    	ratio_max = (msr.lo >> 8) & 0xff;
    }
-	clock_max = ratio_max * SANDYBRIDGE_BCLK + ratio_max / 3;
+	clock_max = ratio_max * NEHALEM_BCLK + ratio_max / 3;

/* Calculate CPU TDP in mW */
    power_max = 25000;
@@ -298,7 +298,7 @@ static int generate_P_state_entries(int core, int cores_per_package)

/* Calculate power at this ratio */
    	power = calculate_power(power_max, ratio_max, ratio);
-		clock = ratio * SANDYBRIDGE_BCLK + ratio / 3;
+		clock = ratio * NEHALEM_BCLK + ratio / 3;

len_pss += acpigen_write_PSS_package(
    		clock,			/*MHz*/
diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h
index 18a45d8..f9dc7e8 100644
--- a/src/cpu/intel/model_2065x/model_2065x.h
+++ b/src/cpu/intel/model_2065x/model_2065x.h
@@ -22,8 +22,8 @@
 #ifndef _CPU_INTEL_MODEL_2065X_H
 #define _CPU_INTEL_MODEL_2065X_H

-/* SandyBridge/IvyBridge bus clock is fixed at 100MHz */
-#define SANDYBRIDGE_BCLK		133
+/* Nehalem bus clock is fixed at 133MHz */
+#define NEHALEM_BCLK		133

#define IA32_FEATURE_CONTROL		0x3a
 #define  CPUID_VMX			(1 << 5)
diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c
index 4c88e44..0fd1bf0 100644
--- a/src/cpu/intel/model_2065x/model_2065x_init.c
+++ b/src/cpu/intel/model_2065x/model_2065x_init.c
@@ -311,7 +311,7 @@ static void set_max_ratio(void)
    wrmsr(IA32_PERF_CTL, perf_ctl);

printk(BIOS_DEBUG, "model_x06ax: frequency set to %d\n",
-	       ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK);
+	       ((perf_ctl.lo >> 8) & 0xff) * NEHALEM_BCLK);
 }

static void set_energy_perf_bias(u8 policy)
diff --git a/src/cpu/intel/model_2065x/tsc_freq.c b/src/cpu/intel/model_2065x/tsc_freq.c
index 7d388be..1c20e29 100644
--- a/src/cpu/intel/model_2065x/tsc_freq.c
+++ b/src/cpu/intel/model_2065x/tsc_freq.c
@@ -27,5 +27,5 @@ unsigned long tsc_freq_mhz(void)
    msr_t platform_info;

platform_info = rdmsr(MSR_PLATFORM_INFO);
-	return SANDYBRIDGE_BCLK * ((platform_info.lo >> 8) & 0xff);
+	return NEHALEM_BCLK * ((platform_info.lo >> 8) & 0xff);
 }