Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32175 )
Change subject: soc/intel/cannonlake: Correct the GPE DWx mapping for GPIO groups ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/32175/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32175/1//COMMIT_MSG@14 PS1, Line 14: Verified the GPIO MISCFG is getting set as per updated map.
TPM was working fine earlier as well so we were just getting lucky that DW1_21 was set all the time […]
TPM was working fine earlier as well so we were just getting lucky that DW1_21 was set all the time and so it never caused timeouts?
Yes. For the current code(gpio configuration(level, non-invert)), I see the status is set all the time. That is expected too, since the PMC GPIOCFG values are correct and status would just mirror the gpio rx state.
Are you able to clear DW1_21 in GPE_STS and does that take effect? I think you had reported in another issue that DW1_21 stays set all the time?
On setting the RxInv(for both level and edge configuration) Bit the status does get clear and it exists from get_gpe_status, without timer expiry. Otherwise if RxInv is not set the code always exits on timer expiry since sts & mask never gets 0. Will further update.