Hello build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth, Jingle Hsu, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41348
to look at the new patch set (#18).
Change subject: soc/intel/xeon_sp/cpx: display UPDs and CPX-SP specific HOBs ......................................................................
soc/intel/xeon_sp/cpx: display UPDs and CPX-SP specific HOBs
Support display of CPX-SP specific HOBs, and UPD parameters.
Such display is used for FSP debugging purpose. It adds boot time.
Some UPD display log excerpts: UPD values for SiliconInit: 0x04: BifurcationPcie0 0x03: BifurcationPcie1
Some HOB display log excerpts: === FSP HOBs === 0x758df000: hob_list_ptr 0x758df000, 0x00000038 bytes: HOB_TYPE_HANDOFF 0x758df038, 0x00000028 bytes: HOB_TYPE_MEMORY_POOL
Signed-off-by: Jonathan Zhang jonzhang@fb.com Signed-off-by: Reddy Chagam anjaneya.chagam@intel.com Change-Id: I42dd519103cc604d4cfee858f4774bd73c979e77 --- M src/soc/intel/xeon_sp/cpx/Makefile.inc A src/soc/intel/xeon_sp/cpx/hob_display.c M src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h A src/soc/intel/xeon_sp/cpx/upd_display.c 4 files changed, 250 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/41348/18