Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/25663 )
Change subject: device/dram/ddr3: improve XMP support ......................................................................
Patch Set 1:
(5 comments)
https://review.coreboot.org/#/c/25663/1/src/device/dram/ddr3.c File src/device/dram/ddr3.c:
https://review.coreboot.org/#/c/25663/1/src/device/dram/ddr3.c@298 PS1, Line 298: /* Minimum CAS Write Latency Time (tCWLmin) - not present in standard SPD */ over line
https://review.coreboot.org/#/c/25663/1/src/device/dram/ddr3.c@491 PS1, Line 491: dimm->cas_supported = (xmp[4] << 8) + xmp[3]; According to spec 1.1 it's ((xmp[4] << 8) + xmp[3]) & 0x7fff
https://review.coreboot.org/#/c/25663/1/src/device/dram/ddr3.c@515 PS1, Line 515: dimm->tCWL = xmp[5] * mtb;; Remove second semicolon
https://review.coreboot.org/#/c/25663/1/src/device/dram/ddr3.c@516 PS1, Line 516: /* Minimum CMD rate */ "System CMD Rate Mode"
https://review.coreboot.org/#/c/25663/1/src/include/device/dram/ddr3.h File src/include/device/dram/ddr3.h:
https://review.coreboot.org/#/c/25663/1/src/include/device/dram/ddr3.h@166 PS1, Line 166: u32 tCMD; u16 should be sufficient