Attention is currently required from: Paul Menzel, Arthur Heymans. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56339 )
Change subject: asrock/e3c246d4i: Add Intel Coffee Lake board ......................................................................
Patch Set 7:
(2 comments)
File src/mainboard/asrock/e3c246d4i/gpio.c:
https://review.coreboot.org/c/coreboot/+/56339/comment/0256294d_b7a3f5e9 PS4, Line 16: /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */
Comments should be trimmed […]
See purism/librem_cnl
File src/mainboard/asrock/e3c246d4i/romstage.c:
https://review.coreboot.org/c/coreboot/+/56339/comment/4154f2e9_2a21b4f0 PS4, Line 26: 50
Out of curiosity, where does this 50 come from? […]
In CB:37441 I used 60 for the X11SCH-F, I'd use the same value here. The oryp5 uses 50 because it only has one DIMM per channel. On Haswell, the RdOdt target defaults to 50, and is increased to 60 when any channel contains 2 DIMMs.