Aaron Durbin (adurbin@chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17214
-gerrit
commit f91099801a38aa2ba32b45d0b34586e38897c50e Author: Aaron Durbin adurbin@chromium.org Date: Thu Nov 3 08:34:23 2016 -0500
reef: tune tpm i2c frequency to 400kHz
This brings the frequency down to 400kHz which is spec for fast i2c.
BUG=chrome-os-partner:58889
Change-Id: I8689a062b5457aa431eaa7fb688a7170dad83fcf Signed-off-by: Aaron Durbin adurbin@chromium.org --- src/mainboard/google/reef/variants/baseboard/devicetree.cb | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index 30d61f6..559b007 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -71,8 +71,18 @@ chip soc/intel/apollolake register "gpe0_dw2" = "PMC_GPE_N_63_32" register "gpe0_dw3" = "PMC_GPE_SW_31_0"
- # Enable I2C2 bus early for TPM access - register "i2c[2].early_init" = "1" + # Enable I2C2 bus early for TPM access and configure as 400kHz + # with manually tuned values. + register "i2c[2]" = "{ + .early_init = 1, + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 0xd0, + .scl_hcnt = 0x68, + .sda_hold = 0x27, + } + }"
# Minimum SLP S3 assertion width 28ms. register "slp_s3_assertion_width_usecs" = "28000"