Naresh Solanki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80666?usp=email )
Change subject: soc/intel/xeon_sp/spr: Set _STA for each IIO stack ......................................................................
soc/intel/xeon_sp/spr: Set _STA for each IIO stack
Set _STA in SSDT based on stack enable. This is to fix below kernel error messages: [Firmware Bug]: no secondary bus range in _CRS
TEST=Build for ibm/sbp1 & made sure 44 Firmware Bug instance resolved.
Change-Id: I2b10504e9db7194380a90fa90f5fbd47ae4f742f Signed-off-by: Naresh Solanki naresh.solanki@9elements.com --- M src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl M src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl M src/soc/intel/xeon_sp/spr/soc_acpi.c 3 files changed, 29 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/80666/1
diff --git a/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl b/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl index 80b3da2..0594150 100644 --- a/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl +++ b/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl @@ -18,10 +18,6 @@ }) Name (_UID, IIO_DEVICE_UID(DEVPREFIX, SOCKET, STACK)) External (_SB.IIO_DEVICE_NAME(STPREFIX, SOCKET, STACK)) - Method (_STA, 0, NotSerialized) // _STA: Status - { - Return (_SB.IIO_DEVICE_NAME(STPREFIX, SOCKET, STACK)) - } Method (_PRT, 0, NotSerialized) { Return (_SB.PRTID) diff --git a/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl b/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl index c65b699..4a93c1a 100644 --- a/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl +++ b/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl @@ -14,10 +14,6 @@ Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) Name (_UID, IIO_DEVICE_UID(DEVPREFIX, SOCKET, STACK)) External (_SB.IIO_DEVICE_NAME(STPREFIX, SOCKET, STACK)) - Method (_STA, 0, NotSerialized) - { - Return (_SB.IIO_DEVICE_NAME(STPREFIX, SOCKET, STACK)) - } Method (_PRT, 0, NotSerialized) { Return (_SB.PRTID) diff --git a/src/soc/intel/xeon_sp/spr/soc_acpi.c b/src/soc/intel/xeon_sp/spr/soc_acpi.c index ca1cdf9..cc17ba0 100644 --- a/src/soc/intel/xeon_sp/spr/soc_acpi.c +++ b/src/soc/intel/xeon_sp/spr/soc_acpi.c @@ -66,6 +66,15 @@ char tres[16]; snprintf(tres, sizeof(tres), "\_SB.PC%d%X", socket, stack); acpigen_write_scope(tres); + + if (stack_enabled) + acpigen_write_STA(0xf); + else { + acpigen_write_STA(0); + acpigen_pop_len(); + return; + } + acpigen_write_name("_CRS");
printk(BIOS_DEBUG, "\tCreating ResourceTemplate %s for socket: %d, stack: %d\n", tres, @@ -145,7 +154,19 @@ /* write _CRS scope */ char tres[16]; snprintf(tres, sizeof(tres), "\_SB.CX%d%X", socket, stack); + + if (stack == 0) + return; + acpigen_write_scope(tres); + if (stack_enabled && is_iio_cxl_stack_res(ri)) + acpigen_write_STA(0xf); + else { + acpigen_write_STA(0); + acpigen_pop_len(); + return; + } + acpigen_write_name("_CRS");
printk(BIOS_DEBUG, "\tCreating ResourceTemplate %s for socket: %d, stack: %d\n", tres, @@ -255,8 +276,12 @@
/* Note, some SKU doesn't provide CPM1 and HQM1 and owns smaller bus ranges accordingly*/ - if (bus_limit > ri->BusLimit) + if (bus_limit > ri->BusLimit) { + acpigen_write_scope(tres); + acpigen_write_STA(0); + acpigen_pop_len(); continue; + }
printk(BIOS_DEBUG, "\tCreating Dino ResourceTemplate %s for socket: %d, " @@ -264,6 +289,7 @@ tres, socket, stack, bus_base, bus_limit);
acpigen_write_scope(tres); + acpigen_write_STA(0xf); acpigen_write_name("_CRS"); acpigen_write_resourcetemplate_header();
@@ -376,9 +402,8 @@
if (stack <= IioStack5) { // TYPE_UBOX_IIO create_dsdt_iou_pci_resource(socket, stack, ri, stack_enabled); - if (is_iio_cxl_stack_res(ri)) - create_dsdt_iou_cxl_resource(socket, stack, ri, - stack_enabled); + create_dsdt_iou_cxl_resource(socket, stack, ri, stack_enabled); + create_dsdt_stack_sta(socket, stack, ri, stack_enabled); } else if (stack >= IioStack8 && stack <= IioStack11) { // TYPE_DINO create_dsdt_ioat_resource(socket, stack, ri, stack_enabled);