[coreboot-gerrit] Change in coreboot[master]: sumeet: add dptf support for SKUs

[Sumeet R Pawnikar (Code Review)]

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44941 )

Change subject: sumeet: add dptf support for SKUs
......................................................................

sumeet: add dptf support for SKUs

i3 i5 i7 sku support

Change-Id: Id42ef25c940795ee323e2a10b92c11c8b6ff7030
Signed-off-by: Sumeet R Pawnikar 
---
M src/mainboard/google/volteer/variants/baseboard/devicetree.cb
A src/soc/intel/common/block/dptf/dptf.c
A src/soc/intel/common/block/include/intelblocks/dptf.h
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/systemagent.c
5 files changed, 83 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/44941/1

diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index ffae2f0..bb295ea 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -376,6 +376,20 @@
    			register "options.fan.fine_grained_control" = "1"
    			register "options.fan.step_size" = "2"

+				## Tuned settings DPTF parameters for core_i3
+				register "soc_dptf_config[INTEL_CORE_i3]" = "{
+					.tdp_pl4 = 105,
+				}"
+
+				## Tuned settings DPTF parameters for core_i5
+				register "soc_dptf_config[INTEL_CORE_i5]" = "{
+					.tdp_pl4 = 107,
+				}"
+
+				## Tuned settings DPTF parameters for core_i7
+				register "soc_dptf_config[INTEL_CORE_i7]" = "{
+				}"
+
    			device generic 0 on end
    		end
    	end # DPTF				0x9A03
diff --git a/src/soc/intel/common/block/dptf/dptf.c b/src/soc/intel/common/block/dptf/dptf.c
new file mode 100644
index 0000000..8fc9694
--- /dev/null
+++ b/src/soc/intel/common/block/dptf/dptf.c
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+//#include <string.h>
+//#include <arch/cpu.h>
+//#include <device/device.h>
+
+#include <cpu/x86/name.h>
+
+#define INTEL_CORE_i3   0
+#define INTEL_CORE_i5   1
+#define INTEL_CORE_i7   2
+#define INTEL_CELERON   3
+#define INTEL_PENTIUM   4
+#define INTEL_SOC_MAX   5
+soc_dptf_config[INTEL_CORE_i3]
+
+//static char cpu_name[49];
+static char processor_name[49];
+
+static sturct {
+	u32 skuid;
+	const char *name;
+} sku_table[] = {
+	{ SKUID_I3, "i3 SKU" },
+	{ SKUID_I5, "i5 SKU" },
+	{ SKUID_I7, "i7 SKU" },
+	{ SKUID_CELERON, "Celeron SKU" },
+	{ SKUID_PENTIUM, "Pentium SKU" },
+};
+
+
+void set_dptf_config (void)
+{
+	u32 sku_id;
+
+// Get Processor SKU name [i3,i5,i7,celeron,pentium]
+// Also, we can refer "Model name"
+// e.g. Intel(R) Core(TM) i5-10310U CPU @ 1.70GHz
+// e.g. Intel(R) Celeron(R) N4020 CPU @ 1.10GHz
+	/* Print processor name */
+	fill_processor_name(processor_name);
+	printk(BIOS_INFO, "CPU: %s.\n", processor_name);
+
+	//cpu_id = cpu_get_cpuid();
+	sku_id = cpu_get_cpuid();
+
+    /* Look for string to match the name */
+    //for (i = 0; i < ARRAY_SIZE(cpu_table); i++) {
+    for (i = 0; i < ARRAY_SIZE(sku_table); i++) {
+        //if (cpu_table[i].cpuid == cpu_id) {
+        if (sku_table[i].skuid == sku_id) {
+            //cpu_type = cpu_table[i].name;
+            sku_type = sku_table[i].name;
+            break;
+        }
+    }
diff --git a/src/soc/intel/common/block/include/intelblocks/dptf.h b/src/soc/intel/common/block/include/intelblocks/dptf.h
new file mode 100644
index 0000000..dccb1eb
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/dptf.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+
+
+#define INTEL_CORE_i3	0
+#define INTEL_CORE_i5	1
+#define INTEL_CORE_i7	2
+#define INTEL_SOC_MAX	3
+soc_dptf_config[INTEL_CORE_i3]
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 2da63ed..d12ad43 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -75,6 +75,9 @@
    /* Common struct containing soc config data required by common code */
    struct soc_intel_common_config common_soc_config;

+	/* SoC specific dptf configuration parameters information */
+	struct soc_intel_common_config soc_dptf_config[INTEL_SOC_MAX];
+
    /* Common struct containing power limits configuration information */
    struct soc_power_limits_config power_limits_config[POWER_LIMITS_MAX];

diff --git a/src/soc/intel/tigerlake/systemagent.c b/src/soc/intel/tigerlake/systemagent.c
index 29487a8..e43ac33 100644
--- a/src/soc/intel/tigerlake/systemagent.c
+++ b/src/soc/intel/tigerlake/systemagent.c
@@ -97,6 +97,7 @@
    }

set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
+	set_dptf_config();
 }

uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz)