[coreboot-gerrit] Change in coreboot[master]: soc/intel/baytrail/lpe.c: Align with Braswell

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43194 )

Change subject: soc/intel/baytrail/lpe.c: Align with Braswell
......................................................................

soc/intel/baytrail/lpe.c: Align with Braswell

This reduces the differences between Bay Trail and Braswell.

Tested with BUILD_TIMELESS=1, Google Ninja remains identical.

Change-Id: If75b4299918f5bee3cc68bc662d03f1a819aef68
Signed-off-by: Angel Pons 
---
M src/soc/intel/baytrail/lpe.c
1 file changed, 5 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/43194/1

diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c
index e31e15e..29633e5 100644
--- a/src/soc/intel/baytrail/lpe.c
+++ b/src/soc/intel/baytrail/lpe.c
@@ -44,11 +44,12 @@
    static const struct reg_script ops[] = {
    	/* Disable PCI interrupt, enable Memory and Bus Master */
    	REG_PCI_OR16(PCI_COMMAND,
-			     PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)),
+			     PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INT_DISABLE),
+
    	/* Enable ACPI mode */
    	REG_IOSF_OR(IOSF_PORT_0x58, LPE_PCICFGCTR1,
-			    LPE_PCICFGCTR1_PCI_CFG_DIS |
-			    LPE_PCICFGCTR1_ACPI_INT_EN),
+			    LPE_PCICFGCTR1_PCI_CFG_DIS | LPE_PCICFGCTR1_ACPI_INT_EN),
+
    	REG_SCRIPT_END
    };
    struct global_nvs *gnvs;
@@ -123,7 +124,7 @@
    }

/* Continue using old way of informing firmware address / size. */
-	pci_write_config32(dev, FIRMWARE_PCI_REG_BASE, res->base);
+	pci_write_config32(dev, FIRMWARE_PCI_REG_BASE,   res->base);
    pci_write_config32(dev, FIRMWARE_PCI_REG_LENGTH, res->size);

/* C0 and later steppings use an offset in the MMIO space. */