[coreboot-gerrit] New patch to review for coreboot: Add SoC specific microcode update check in ramstage

[Patrick Georgi]

Patrick Georgi ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11055

-gerrit

commit 3d9c72ee7ef82d69b5186d40e6c742a7b7b878cf
Author: Rizwan Qureshi 
Date:   Thu Jul 23 22:31:51 2015 +0530

Add SoC specific microcode update check in ramstage

Some Intel SoCs which support SGX feature, report the
    microcode patch revision one less than the actual revision.
    This results in the same microcode patch getting loaded again.
    Add a SoC specific check to avoid relading the same patch.

BUG=chrome-os-partner:42046
    BRANCH=None
    TEST=Built for glados and tested on RVP3
    CQ-DEPEND=CL:286054

Change-Id: Iab4c34c6c55119045947f598e89352867c67dcb8
    Signed-off-by: Patrick Georgi 
    Original-Commit-Id: ab2ed73db3581cd432f9bc84acca47f5e53a0e9b
    Original-Change-Id: I4f7bf9c841e5800668208c11b0afcf8dba48a775
    Original-Signed-off-by: Rizwan Qureshi 
    Original-Reviewed-on: https://chromium-review.googlesource.com/287513
    Original-Reviewed-by: Aaron Durbin 
---
 src/cpu/intel/microcode/microcode.c | 16 ++++++++++++++++
 src/include/cpu/intel/microcode.h   |  4 ++++
 2 files changed, 20 insertions(+)

diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c
index 3492bfd..1ee1299 100644
--- a/src/cpu/intel/microcode/microcode.c
+++ b/src/cpu/intel/microcode/microcode.c
@@ -28,6 +28,7 @@
 #include <cpu/cpu.h>
 #include <cpu/x86/msr.h>
 #include <cpu/intel/microcode.h>
+#include <rules.h>

#if !defined(__PRE_RAM__)
 #include <cbfs.h>
@@ -95,6 +96,14 @@ void intel_microcode_load_unlocked(const void *microcode_patch)
    if (current_rev == m->rev)
    	return;

+#if ENV_RAMSTAGE
+	/*SoC specific check to update microcode*/
+	if (soc_ucode_update_required(current_rev, m->rev) < 0) {
+		printk(BIOS_DEBUG, "Skip microcode update\n");
+		return;
+	}
+#endif
+
    msr.lo = (unsigned long)m + sizeof(struct microcode);
    msr.hi = 0;
    wrmsr(0x79, msr);
@@ -202,3 +211,10 @@ void intel_update_microcode_from_cbfs(void)
    spin_unlock(&microcode_lock);
 #endif
 }
+
+#if ENV_RAMSTAGE
+__attribute__((weak)) int soc_ucode_update_required(u32 currrent_patch_id, u32 new_patch_id)
+{
+	return 0;
+}
+#endif
diff --git a/src/include/cpu/intel/microcode.h b/src/include/cpu/intel/microcode.h
index d2fa1b7..d951a63 100644
--- a/src/include/cpu/intel/microcode.h
+++ b/src/include/cpu/intel/microcode.h
@@ -29,6 +29,10 @@ const void *intel_microcode_find(void);
  * well as ensuring the microcode matches the family and revision (i.e. with
  * intel_microcode_find()). */
 void intel_microcode_load_unlocked(const void *microcode_patch);
+
+/* SoC specific check to determine if microcode update is really
+ * required, return value of < 0 will skip microcode update. */
+int soc_ucode_update_required(u32 currrent_patch_id, u32 new_patch_id);
 #endif

#endif