Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/25595
Change subject: nb/intel/i945: Use common SMM_TSEG code ......................................................................
nb/intel/i945: Use common SMM_TSEG code
Use the common SMM_TSEG code to relocate the smihandler to TSEG.
Change-Id: I0e6374746c3df96ce16f1c4a177af12747d6c1a9 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/model_106cx/Kconfig M src/cpu/intel/model_106cx/Makefile.inc M src/cpu/intel/model_6ex/Kconfig M src/cpu/intel/model_6ex/Makefile.inc M src/cpu/intel/model_f3x/Kconfig M src/cpu/intel/model_f3x/Makefile.inc M src/cpu/intel/model_f4x/Kconfig M src/cpu/intel/model_f4x/Makefile.inc M src/northbridge/intel/i945/Kconfig M src/northbridge/intel/i945/i945.h M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/i945/ram_calc.c M src/southbridge/intel/i82801gx/Makefile.inc 13 files changed, 51 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/25595/1
diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index f365cf1..0cb47da 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -13,6 +13,7 @@ select SUPPORT_CPU_UCODE_IN_CBFS select SERIALIZED_SMM_INITIALIZATION select CPU_INTEL_COMMON + select HAS_NO_SMRR
if CPU_INTEL_MODEL_106CX
diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc index cd753db..0703099 100644 --- a/src/cpu/intel/model_106cx/Makefile.inc +++ b/src/cpu/intel/model_106cx/Makefile.inc @@ -1,5 +1,6 @@ ramstage-y += model_106cx_init.c subdirs-y += ../../x86/name subdirs-y += ../common +subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_106cx/microcode.bin diff --git a/src/cpu/intel/model_6ex/Kconfig b/src/cpu/intel/model_6ex/Kconfig index 10ebcc7..df1cbbb 100644 --- a/src/cpu/intel/model_6ex/Kconfig +++ b/src/cpu/intel/model_6ex/Kconfig @@ -11,3 +11,4 @@ select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_COMMON + select HAS_NO_SMRR diff --git a/src/cpu/intel/model_6ex/Makefile.inc b/src/cpu/intel/model_6ex/Makefile.inc index 4321f2a..13e08f0 100644 --- a/src/cpu/intel/model_6ex/Makefile.inc +++ b/src/cpu/intel/model_6ex/Makefile.inc @@ -1,5 +1,6 @@ ramstage-y += model_6ex_init.c subdirs-y += ../../x86/name subdirs-y += ../common +subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6ex/microcode.bin diff --git a/src/cpu/intel/model_f3x/Kconfig b/src/cpu/intel/model_f3x/Kconfig index 7eaa820..0c6da97 100644 --- a/src/cpu/intel/model_f3x/Kconfig +++ b/src/cpu/intel/model_f3x/Kconfig @@ -6,3 +6,4 @@ select ARCH_RAMSTAGE_X86_32 select SMP select SUPPORT_CPU_UCODE_IN_CBFS + select HAS_NO_SMRR diff --git a/src/cpu/intel/model_f3x/Makefile.inc b/src/cpu/intel/model_f3x/Makefile.inc index b73a25d..7367914 100644 --- a/src/cpu/intel/model_f3x/Makefile.inc +++ b/src/cpu/intel/model_f3x/Makefile.inc @@ -1,3 +1,4 @@ ramstage-y += model_f3x_init.c +subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f3x/microcode.bin diff --git a/src/cpu/intel/model_f4x/Kconfig b/src/cpu/intel/model_f4x/Kconfig index 4ef60b5..c1e0dfd 100644 --- a/src/cpu/intel/model_f4x/Kconfig +++ b/src/cpu/intel/model_f4x/Kconfig @@ -6,3 +6,4 @@ select ARCH_RAMSTAGE_X86_32 select SMP select SUPPORT_CPU_UCODE_IN_CBFS + select HAS_NO_SMRR diff --git a/src/cpu/intel/model_f4x/Makefile.inc b/src/cpu/intel/model_f4x/Makefile.inc index 9aeb107..2f11d7f 100644 --- a/src/cpu/intel/model_f4x/Makefile.inc +++ b/src/cpu/intel/model_f4x/Makefile.inc @@ -1,3 +1,4 @@ ramstage-y += model_f4x_init.c +subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f4x/microcode.bin diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 482f98a..dcf3fb5 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -28,6 +28,7 @@ select RELOCATABLE_RAMSTAGE select INTEL_EDID select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT + select SMM_TSEG
config NORTHBRIDGE_INTEL_SUBTYPE_I945GC def_bool n diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index cc5f087..100ac9a 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -366,6 +366,7 @@
u32 decode_igd_memory_size(u32 gms); u32 decode_tseg_size(const u8 esmramc); +uintptr_t smm_region_start(void);
#endif /* __ACPI__ */
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 37f94b1..94f7dac 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -24,6 +24,7 @@ #include <cbmem.h> #include <cpu/cpu.h> #include <arch/acpi.h> +#include <cpu/intel/smm/gen1/smi.h> #include "i945.h"
static int get_pcie_bar(u32 *base) @@ -118,6 +119,43 @@ assign_resources(dev->link_list); }
+u32 northbridge_get_tseg_size(void) +{ + const u8 esmramc = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), + ESMRAMC); + return decode_tseg_size(esmramc); +} + +u32 northbridge_get_tseg_base(void) +{ + return (u32) smm_region_start(); +} + +void northbridge_write_smram(u8 smram) +{ + pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, smram); +} + +/* + * Really doesn't belong here but will go away with parallel mp init, + * so let it be here for a while... + */ +int cpu_get_apic_id_map(int *apic_id_map) +{ + unsigned int i; + + /* Logical processors (threads) per core */ + const struct cpuid_result cpuid1 = cpuid(1); + /* Read number of cores. */ + const char cores = (cpuid1.ebx >> 16) & 0xf; + + /* TODO in parallel MP cpuid(1).ebx */ + for (i = 0; i < cores; i++) + apic_id_map[i] = i; + + return cores; +} + /* TODO We could determine how many PCIe busses we need in * the bar. For now that number is hardcoded to a max of 64. * See e7525/northbridge.c for an example. diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c index 5f3513a..aeace48 100644 --- a/src/northbridge/intel/i945/ram_calc.c +++ b/src/northbridge/intel/i945/ram_calc.c @@ -43,7 +43,7 @@ } }
-static uintptr_t smm_region_start(void) +uintptr_t smm_region_start(void) { uintptr_t tom;
diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc index bb68d93..70abbe2 100644 --- a/src/southbridge/intel/i82801gx/Makefile.inc +++ b/src/southbridge/intel/i82801gx/Makefile.inc @@ -33,8 +33,10 @@ ramstage-y += reset.c ramstage-y += watchdog.c
+ifneq ($(CONFIG_SMM_TSEG),y) ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S +endif smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
romstage-y += early_smbus.c early_lpc.c