[coreboot-gerrit] [M] Change in coreboot[main]: soc/intel/alderlake: Add function to force disable memory channels

[Jamie Chen (Code Review)]

Attention is currently required from: Christian Walter, Dinesh Gehlot, Eric Lai, Jayvik Desai, Jeremy Soller, Kapil Porwal, Lean Sheng Tan, Michał Kopeć, Michał Żygowski, Nick Vaccaro, Paul Menzel, Piotr Król, Sean Rhodes, Subrata Banik, Tim Crawford.

Jamie Chen has posted comments on this change by Kapil Porwal. ( https://review.coreboot.org/c/coreboot/+/85529?usp=email )

Change subject: soc/intel/alderlake: Add function to force disable memory channels
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Patch Set 7:

(1 comment)

File src/soc/intel/alderlake/meminit.c:

https://review.coreboot.org/c/coreboot/+/85529/comment/28c38b0f_1c92b76a?usp... :
PS1, Line 252: 	if (ch_disable_mask == 0) {
> Are these combinations valid? […]
> Are these combinations valid?
>
> Mc0Ch1
> Mc0Ch3

Invalid.
> I wonder if the channels are grouped in pairs (0+1 and 2+3), and the first >channel of a group must be enabled if the group is in use.

One LP5/x DRAM chip usually has two 16 bits channels. We can connect Mc0Ch0-1 to one DRAM chip and connect Mc0Ch2-3 to another DRAM chip.
> Per my test, the four combinations are valid.
> I also tried Mc0Ch0+Mc0Ch1+Mc0Ch2 and Mc0Ch0+Mc0Ch2+Mc0Ch3 combinations are work >as well.
> It looks like the first channel of every dram chip must be turn on.
>
> I will check with internal team if it is a necessary condition?

After consulting our memory expert, the first channel of DRAM chip must be connected.