[coreboot-gerrit] [M] Change in coreboot[master]: mb/google/brya/gaelin: Change DDR4 from interleave to non-interleave

[Werner Zeh (Code Review)]

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68806 )

Change subject: mb/google/brya/gaelin: Change DDR4 from interleave to non-interleave
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mb/google/brya/gaelin: Change DDR4 from interleave to non-interleave

The brask DDR4 is set to interleave, due to the limited number of
gaelin PCB layers and the traces need to be smooth,
we will use non-interleave for gaelin DDR4.

BUG=b:255399229, b:249000573
BRANCH=firmware-brya-14505.B
TEST=Build "emerge-brask coreboot" and pass MRC memory training

Change-Id: I34413343e3f7c283f49fbbdd277d9da39c09f9f8
Signed-off-by: Raymond Chung 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68806
Tested-by: build bot (Jenkins) 
Reviewed-by: Derek Huang 
Reviewed-by: Zhuohao Lee 
---
A src/mainboard/google/brya/variants/gaelin/Makefile.inc
A src/mainboard/google/brya/variants/gaelin/memory.c
2 files changed, 63 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Zhuohao Lee: Looks good to me, approved
  Raymond Chung: Looks good to me, but someone else must approve
  Derek Huang: Looks good to me, but someone else must approve

diff --git a/src/mainboard/google/brya/variants/gaelin/Makefile.inc b/src/mainboard/google/brya/variants/gaelin/Makefile.inc
new file mode 100644
index 0000000..fd45b94
--- /dev/null
+++ b/src/mainboard/google/brya/variants/gaelin/Makefile.inc
@@ -0,0 +1 @@
+romstage-y += memory.c
diff --git a/src/mainboard/google/brya/variants/gaelin/memory.c b/src/mainboard/google/brya/variants/gaelin/memory.c
new file mode 100644
index 0000000..98b655c
--- /dev/null
+++ b/src/mainboard/google/brya/variants/gaelin/memory.c
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <soc/romstage.h>
+
+static const struct mb_cfg ddr4_mem_config = {
+	.type = MEM_TYPE_DDR4,
+
+	.rcomp = {
+		/* Baseboard uses only 100ohm Rcomp resistors */
+		.resistor = 100,
+
+		/* Baseboard Rcomp target values */
+		.targets = {50, 20, 25, 25, 25},
+	},
+
+	.ect = 1, /* Early Command Training */
+
+	.UserBd = BOARD_TYPE_MOBILE,
+
+	.ddr_config = {
+		.dq_pins_interleaved = false,
+	},
+};
+
+const struct mb_cfg *variant_memory_params(void)
+{
+	return &ddr4_mem_config;
+}
+
+void variant_get_spd_info(struct mem_spd *spd_info)
+{
+	spd_info->topo = MEM_TOPO_DIMM_MODULE;
+	spd_info->smbus[0].addr_dimm[0] = 0x50;
+	spd_info->smbus[0].addr_dimm[1] = 0x51;
+	spd_info->smbus[1].addr_dimm[0] = 0x52;
+	spd_info->smbus[1].addr_dimm[1] = 0x53;
+}