the following patch was just integrated into master: commit a7cac0c21d85e651caaab2af7f8f1a7263e8abb9 Author: Patrick Georgi pgeorgi@chromium.org Date: Fri Feb 19 17:33:26 2016 +0100
soc/*: fix uart's regwidth specification in cbtables
coreboot passes information about the serial port implementation to payloads through a cbtables entry. We set the register width to 1 on most SoCs because that looked as good a default as any, but checking the uart structs they use, it's 4 for all of them.
Change-Id: I9848f79737106dc32f864ca901c0bc48f489e6b8 Signed-off-by: Patrick Georgi pgeorgi@chromium.org Reviewed-on: https://review.coreboot.org/13746 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner jwerner@chromium.org
See https://review.coreboot.org/13746 for details.
-gerrit