Ronald G. Minnich (rminnich@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3242
-gerrit
commit e70f90c125b86bd968e82b1a22a4116bbd6e14bf Author: Paul Menzel paulepanter@users.sourceforge.net Date: Wed May 8 17:08:55 2013 +0200
Clean up usage of multiply_to_tsc
multiply_to_tsc was being copied everywhere, which is bad practice. Put it in the tsc.h include file where it belongs. Delete the copies of it.
We will leave it to secunet to tell us if they want a copyright notice on a piece of code that gets implemented all over the place; we need not make this decision for them.
This might be a good time to get a copyright notice into tsc.h anyway.
Change-Id: Ied0013ad4b1a9e5e2b330614bb867fd806f9a407 Signed-off-by: Paul Menzel paulepanter@users.sourceforge.net Signed-off-by: Ronald G. Minnich rminnich@gmail.com --- src/include/cpu/x86/tsc.h | 13 +++++++++++++ src/northbridge/intel/gm45/delay.c | 12 ------------ src/northbridge/intel/i5000/udelay.c | 12 ------------ src/northbridge/intel/i945/udelay.c | 12 ------------ src/northbridge/intel/sandybridge/udelay.c | 13 ------------- 5 files changed, 13 insertions(+), 49 deletions(-)
diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h index 8e49a66..66451ad 100644 --- a/src/include/cpu/x86/tsc.h +++ b/src/include/cpu/x86/tsc.h @@ -27,6 +27,19 @@ static inline tsc_t rdtsc(void) }
#if !defined(__ROMCC__) +/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. + * This code is used to prevent use of libgcc's umoddi3. + */ +static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b) +{ + tsc->lo = (a & 0xffff) * (b & 0xffff); + tsc->hi = ((tsc->lo >> 16) + + ((a & 0xffff) * (b >> 16)) + + ((b & 0xffff) * (a >> 16))); + tsc->lo = ((tsc->hi & 0xffff) << 16) | (tsc->lo & 0xffff); + tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16); +} + /* Too many registers for ROMCC */ static inline unsigned long long rdtscll(void) { diff --git a/src/northbridge/intel/gm45/delay.c b/src/northbridge/intel/gm45/delay.c index 9f49c6e..a861e25 100644 --- a/src/northbridge/intel/gm45/delay.c +++ b/src/northbridge/intel/gm45/delay.c @@ -2,7 +2,6 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2008 coresystems GmbH - * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,17 +23,6 @@ #include <cpu/intel/speedstep.h> #include "delay.h"
-/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. */ -static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b) -{ - tsc->lo = (a & 0xffff) * (b & 0xffff); - tsc->hi = ((tsc->lo >> 16) - + ((a & 0xffff) * (b >> 16)) - + ((b & 0xffff) * (a >> 16))); - tsc->lo = ((tsc->hi & 0xffff) << 16) | (tsc->lo & 0xffff); - tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16); -} - /** * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock */ diff --git a/src/northbridge/intel/i5000/udelay.c b/src/northbridge/intel/i5000/udelay.c index 3768e16..f57f320 100644 --- a/src/northbridge/intel/i5000/udelay.c +++ b/src/northbridge/intel/i5000/udelay.c @@ -2,7 +2,6 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2008 coresystems GmbH - * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,17 +23,6 @@ #include <cpu/x86/msr.h> #include <cpu/intel/speedstep.h>
-/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. */ -static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b) -{ - tsc->lo = (a & 0xffff) * (b & 0xffff); - tsc->hi = ((tsc->lo >> 16) - + ((a & 0xffff) * (b >> 16)) - + ((b & 0xffff) * (a >> 16))); - tsc->lo = ((tsc->hi & 0xffff) << 16) | (tsc->lo & 0xffff); - tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16); -} - /** * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock */ diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c index 780c730..3d5d6c6 100644 --- a/src/northbridge/intel/i945/udelay.c +++ b/src/northbridge/intel/i945/udelay.c @@ -2,7 +2,6 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2008 coresystems GmbH - * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,17 +23,6 @@ #include <cpu/x86/msr.h> #include <cpu/intel/speedstep.h>
-/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. */ -static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b) -{ - tsc->lo = (a & 0xffff) * (b & 0xffff); - tsc->hi = ((tsc->lo >> 16) - + ((a & 0xffff) * (b >> 16)) - + ((b & 0xffff) * (a >> 16))); - tsc->lo = ((tsc->hi & 0xffff) << 16) | (tsc->lo & 0xffff); - tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16); -} - /** * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock */ diff --git a/src/northbridge/intel/sandybridge/udelay.c b/src/northbridge/intel/sandybridge/udelay.c index 3edd69d..a2ce0d8 100644 --- a/src/northbridge/intel/sandybridge/udelay.c +++ b/src/northbridge/intel/sandybridge/udelay.c @@ -26,19 +26,6 @@ * Intel SandyBridge/IvyBridge CPUs always run the TSC at BCLK=100MHz */
-/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. - * This code is used to prevent use of libgcc's umoddi3. - */ -static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b) -{ - tsc->lo = (a & 0xffff) * (b & 0xffff); - tsc->hi = ((tsc->lo >> 16) - + ((a & 0xffff) * (b >> 16)) - + ((b & 0xffff) * (a >> 16))); - tsc->lo = ((tsc->hi & 0xffff) << 16) | (tsc->lo & 0xffff); - tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16); -} - void udelay(u32 us) { u32 dword;