Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80634?usp=email )
Change subject: soc/intel/xeon_sp: Move MEM_ADDR_64MB_SHIFT_BITS to Xeon-SP ......................................................................
soc/intel/xeon_sp: Move MEM_ADDR_64MB_SHIFT_BITS to Xeon-SP
Move MEM_ADDR_64MB_SHIFT_BITS from FSP headers to Xeon-SP common layer to reduce the dependency.
Change-Id: I4e1a652ad58233f7514cb9b23813d75144b8d435 Signed-off-by: Shuo Liu shuo.liu@intel.com --- M src/soc/intel/xeon_sp/include/soc/util.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h M src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/defs_memmap.h M src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_memmap.h 4 files changed, 2 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/80634/1
diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h index dc02e79..8555789 100644 --- a/src/soc/intel/xeon_sp/include/soc/util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -6,6 +6,8 @@ #include <cpu/x86/msr.h> #include <hob_iiouds.h>
+#define MEM_ADDR_64MB_SHIFT_BITS 26 + void lock_pam0123(void); void unlock_pam_regions(void);
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h index 573b5c3..4a74710 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h @@ -57,7 +57,6 @@ #define MAX_IMC_PER_SOCKET 2
#define MEM_TYPE_RESERVED (1 << 8) -#define MEM_ADDR_64MB_SHIFT_BITS 26
#define NGN_MAX_SERIALNUMBER_STRLEN 4 #define NGN_MAX_PARTNUMBER_STRLEN 20 diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/defs_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/defs_memmap.h index 89897bc..0b8ac73 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/defs_memmap.h +++ b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/defs_memmap.h @@ -46,7 +46,6 @@ #define MEMTYPE_VOLATILE_MASK (MEMTYPE_1LM_MASK | MEMTYPE_2LM_MASK)
#define MEM_TYPE_RESERVED (1 << 8) -#define MEM_ADDR_64MB_SHIFT_BITS 26
//------------------------------------------------------------------------------------ // Uncomment line(s) below to override macro definitions in FSP MemoryMapDataHob.h diff --git a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_memmap.h index c35b2f6..f97056a 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_memmap.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_memmap.h @@ -43,7 +43,6 @@ #define MAX_IMC_PER_SOCKET 2
#define MEM_TYPE_RESERVED (1 << 8) -#define MEM_ADDR_64MB_SHIFT_BITS 26
// // System Memory Map HOB information