Attention is currently required from: Felix Singer, Patrick Rudolph. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52627 )
Change subject: soc/intel/skylake: Clean up root port structs ......................................................................
Patch Set 2: Code-Review+1
(1 comment)
File src/soc/intel/skylake/chip.c:
https://review.coreboot.org/c/coreboot/+/52627/comment/f866b218_bc9340f5 PS2, Line 35: static const struct pcie_rp_group pch_rp_groups[] = { : #if CONFIG(SKYLAKE_SOC_PCH_H) : { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, : { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8 }, : /* Sunrise Point PCH-H actually only has 4 ports in the : third group. But that would require a runtime check : and probing 4 non-existent ports shouldn't hurt. */ : { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8 }, : #else : { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, : { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4 }, : #endif : we already have one PCH with only 4 ports in group 3 (PCIE_2): KBL. we can do the same for -LP like this:
static const struct pcie_rp_group pch_rp_groups[] = { { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8 }, #if CONFIG(SKYLAKE_SOC_PCH_H) /* Sunrise Point PCH-H actually only has 4 ports in the third group. But that would require a runtime check and probing 4 non-existent ports shouldn't hurt. */ { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8 }, #endif { 0 } };
I both cases, KBL-H and SKL/KBL-LP, we'd check 4 ports more then we have, but that doesn't hurt