Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4177
-gerrit
commit 10343e7a43b5e15003ba534816013ae5ba1d1822 Author: Duncan Laurie dlaurie@chromium.org Date: Tue May 21 09:28:28 2013 -0700
slippy: Enable EC SMI
Enable GPIO SMI for GPIO34 and set it as inverted so it is only generated when it is raised by the EC.
1) ec console command: lidopen 2) wait until booted to developer screen 3) ec console command: lidclose 4) ensure system turns off
Change-Id: I7d50f171f3f4539c7c264103d1ffc7c5d0f1c7ba Signed-off-by: Duncan Laurie dlaurie@chromium.org Reviewed-on: https://gerrit.chromium.org/gerrit/56052 Reviewed-by: Aaron Durbin adurbin@chromium.org --- src/mainboard/google/slippy/devicetree.cb | 3 ++- src/southbridge/intel/lynxpoint/lp_gpio.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb index 29c4763..fc6462c 100644 --- a/src/mainboard/google/slippy/devicetree.cb +++ b/src/mainboard/google/slippy/devicetree.cb @@ -49,7 +49,8 @@ chip northbridge/intel/haswell register "gen1_dec" = "0x00fc0801" register "gen2_dec" = "0x00fc0901"
- register "alt_gp_smi_en" = "0x0000" + # EC_SMI is GPIO34 + register "alt_gp_smi_en" = "0x0004" register "gpe0_en_1" = "0x00000000" # EC_SCI is GPIO36 register "gpe0_en_2" = "0x00000010" diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.h b/src/southbridge/intel/lynxpoint/lp_gpio.h index 48a23cb..d9927dc 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.h +++ b/src/southbridge/intel/lynxpoint/lp_gpio.h @@ -110,7 +110,7 @@ .route = GPIO_ROUTE_SCI }
#define LP_GPIO_ACPI_SMI \ - { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, \ + { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, \ .owner = GPIO_OWNER_ACPI, \ .route = GPIO_ROUTE_SMI }