Rory Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59531 )
Change subject: drivers/net/r8168: Add customized_mleds to support RTL8125 ......................................................................
drivers/net/r8168: Add customized_mleds to support RTL8125
The Realtek RTL8125 have four registers for each led, therefore add customized[] to support register array.
BUG=b:193750191 TEST=emerge-brask coreboot chromeos-bootimage
Signed-off-by: Rory Liu rory.liu@quanta.corp-partner.google.com Change-Id: I4b05a859dc0a0d2b8d6b35d6491fc88f7077cb92 --- M src/drivers/net/chip.h M src/drivers/net/r8168.c M src/include/device/pci_ids.h M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/brask/overridetree.cb 5 files changed, 38 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/59531/1
diff --git a/src/drivers/net/chip.h b/src/drivers/net/chip.h index 9b6a4e5..a29def3 100644 --- a/src/drivers/net/chip.h +++ b/src/drivers/net/chip.h @@ -8,6 +8,7 @@
struct drivers_net_config { uint16_t customized_leds; + uint16_t customized_mleds[]; unsigned int wake; /* Wake pin for ACPI _PRW */
/* Does the device have a power resource? */ diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c index 5606859..7b08c54 100644 --- a/src/drivers/net/r8168.c +++ b/src/drivers/net/r8168.c @@ -28,7 +28,8 @@
#define CMD_REG 0x37 #define CMD_REG_RESET 0x10 -#define CMD_LED0_LED1 0x18 +//#define CMD_LED0_LED1 0x18 +#define CMD_LEDSEL[4] {0x18, 0x86, 0x84, 0x96}
#define CFG_9346 0x50 #define CFG_9346_LOCK 0x00 @@ -249,8 +250,19 @@ if (!config) return;
- /* Read the customized LED setting from devicetree */ - printk(BIOS_DEBUG, "r8168: Customized LED 0x%x\n", config->customized_leds); + if (dev->subsystem_device == PCI_DEVICE_ID_REALTEK_8125) { + for (i = 0; i < 4; i++) { + /* Read the customized LED setting from devicetree */ + printk(BIOS_DEBUG, "r8168: Customized LED 0x%x\n", config->customized_mleds[i]); + + /* Set customized LED registers */ + outw(config->customized_mleds[i], io_base + CMD_LEDSEL[i]); + printk(BIOS_DEBUG, "r8168: read back LED setting as 0x%x\n", + inw(io_base + CMD_LEDSEL[i])); + } + } else if (dev->subsystem_device == PCI_DEVICE_ID_REALTEK_8111) { + /* Read the customized LED setting from devicetree */ + printk(BIOS_DEBUG, "r8168: Customized LED 0x%x\n", config->customized_leds);
/* * Refer to RTL8111H datasheet 7.2 Customizable LED Configuration @@ -267,10 +279,11 @@ * FC Bit12 Bit13 Bit14 Bit15 */
- /* Set customized LED registers */ - outw(config->customized_leds, io_base + CMD_LED0_LED1); - printk(BIOS_DEBUG, "r8168: read back LED setting as 0x%x\n", - inw(io_base + CMD_LED0_LED1)); + /* Set customized LED registers */ + outw(config->customized_leds, io_base + CMD_LEDSEL[0]); + printk(BIOS_DEBUG, "r8168: read back LED setting as 0x%x\n", + inw(io_base + CMD_LEDSEL[0])); + } }
static void r8168_init(struct device *dev) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index e820d5a..424ed32 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -1283,8 +1283,9 @@ #define PCI_DEVICE_ID_REALTEK_8029 0x8029 #define PCI_DEVICE_ID_REALTEK_8129 0x8129 #define PCI_DEVICE_ID_REALTEK_8139 0x8139 -#define PCI_DEVICE_ID_REALTEK_8168 0x8168 -#define PCI_DEVICE_ID_REALTEK_8125 0x8125 +#define PCI_DEVICE_ID_REALTEK_8168 0x8168 +#define PCI_DEVICE_ID_REALTEK_8125 0x8125 +#define PCI_DEVICE_ID_REALTEK_8111 0x8111
#define PCI_VENDOR_ID_TYAN 0x10f1 #define PCI_VENDOR_ID_XILINX 0x10ee diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 70729c9..00d0e79 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -7,6 +7,9 @@ config BOARD_GOOGLE_BASEBOARD_BRASK def_bool n select SPD_CACHE_IN_FMAP + select RT8168_GET_MAC_FROM_VPD + select RT8168_SET_LED_MODE +
if BOARD_GOOGLE_BASEBOARD_BRYA || BOARD_GOOGLE_BASEBOARD_BRASK
diff --git a/src/mainboard/google/brya/variants/brask/overridetree.cb b/src/mainboard/google/brya/variants/brask/overridetree.cb index 3805666..3420f58 100644 --- a/src/mainboard/google/brya/variants/brask/overridetree.cb +++ b/src/mainboard/google/brya/variants/brask/overridetree.cb @@ -79,6 +79,17 @@ device generic 0 alias dptf_policy on end end end + device ref pcie_rp7 on + chip drivers/net + register "customized_mleds" = "{ + [0] = 0x0e09, ## 05af + [1] = 0x0e12, + [2] = 0x0e24, + [3] = 0x0e3f + }" + device pci 00.0 on end + end + end # RTL8125 Ethernet NIC device ref pcie4_0 on # Enable CPU PCIE RP 1 using CLK 0 register "cpu_pcie_rp[CPU_RP(1)]" = "{