[coreboot-gerrit] [M] Change in coreboot[master]: soc/intel/{adl,cmn}: Add/Remove LTR disqualification for UFS

[Subrata Banik (Code Review)]

Attention is currently required from: Haribalaraman Ramasubramanian, Reka Norman, Rizwan Qureshi, Tim Wawrzynczak, Daniil Lunev, Meera Ravindranath, Nick Vaccaro, Divagar Mohandass.

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68251 )

Change subject: soc/intel/{adl,cmn}: Add/Remove LTR disqualification for UFS
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Patch Set 8: Code-Review+1

(3 comments)

File src/soc/intel/alderlake/include/soc/ufs.h:

https://review.coreboot.org/c/coreboot/+/68251/comment/f834886c_7df6b7d8 
PS8, Line 26: 0x1B0C
0x1b0c

https://review.coreboot.org/c/coreboot/+/68251/comment/3d8f6eca_18762070 
PS8, Line 27: 0x1E30
0x1e30

File src/soc/intel/common/block/acpi/acpi/ufs.asl:

https://review.coreboot.org/c/coreboot/+/68251/comment/4cc68d93_7ce1ae0d 
PS8, Line 67: PCH_PWRM_BASE_SIZE
nit: won't this fit in line above?