Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34775 )
Change subject: amd/stoneyridge,picasso: Open TSEG earlier ......................................................................
amd/stoneyridge,picasso: Open TSEG earlier
Don't make assumptions about which subregion will be accessed first.
Change-Id: I558fa4acc5068014b3748be6fc1bc34999054c0a Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/soc/amd/picasso/ramtop.c M src/soc/amd/stoneyridge/ramtop.c 2 files changed, 12 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/34775/1
diff --git a/src/soc/amd/picasso/ramtop.c b/src/soc/amd/picasso/ramtop.c index 6b28ec7..672fdd8 100644 --- a/src/soc/amd/picasso/ramtop.c +++ b/src/soc/amd/picasso/ramtop.c @@ -111,6 +111,7 @@
int smm_subregion(int sub, uintptr_t *start, size_t *size) { + static int once; uintptr_t sub_base; size_t sub_size; const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; @@ -118,6 +119,11 @@ smm_region(&sub_base, &sub_size); assert(sub_size > CONFIG_SMM_RESERVED_SIZE);
+ if (!once) { + clear_tvalid(); + once = 1; + } + switch (sub) { case SMM_SUBREGION_HANDLER: /* Handler starts at the base of TSEG. */ @@ -127,7 +133,6 @@ /* External cache is in the middle of TSEG. */ sub_base += sub_size - cache_size; sub_size = cache_size; - clear_tvalid(); break; default: *start = 0; diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c index 26d84ce..e2b0f7d 100644 --- a/src/soc/amd/stoneyridge/ramtop.c +++ b/src/soc/amd/stoneyridge/ramtop.c @@ -111,6 +111,7 @@
int smm_subregion(int sub, uintptr_t *start, size_t *size) { + static int once; uintptr_t sub_base; size_t sub_size; const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; @@ -118,6 +119,11 @@ smm_region(&sub_base, &sub_size); assert(sub_size > CONFIG_SMM_RESERVED_SIZE);
+ if (!once) { + clear_tvalid(); + once = 1; + } + switch (sub) { case SMM_SUBREGION_HANDLER: /* Handler starts at the base of TSEG. */ @@ -127,7 +133,6 @@ /* External cache is in the middle of TSEG. */ sub_base += sub_size - cache_size; sub_size = cache_size; - clear_tvalid(); break; default: *start = 0;