[coreboot-gerrit] [XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock

[Subrata Banik (Code Review)]

Attention is currently required from: Ashish Kumar Mishra, Dinesh Gehlot, Elyes Haouas, Eran Mitrani, Felix Singer, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Saurabh Mishra, Tarun.

Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83354?usp=email )

Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
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Patch Set 36:

(1 comment)

File src/soc/intel/pantherlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/83354/comment/24608e11_aecd79e8?usp... :
PS30, Line 141: 0xfe02c000
> we don't use FSP-T hence, ideally this is not applicable to us.
> > Hi Subrata, yes, so to align the LPSS UART Base Addr b/w FSP and Coreboot, it would be good to have a UPD in FSP-M/S. We are working with FSP Team.

This is what I'm trying to convey is that, we don't need any UPD for UART BAR in FSP-M or FSP-S as long as FSP UPD honor https://review.coreboot.org/c/coreboot/+/83750 CL where we are saying UART0 should be `skip init` meaning, FSP shouldn't bother to touch this. For such scenario, the BAR address that coreboot decides should be enough to get both coreboot and FSP debug prints.