[coreboot-gerrit] Change in coreboot[master]: soc/intel/jsl: Add CdClock/SkipCdClockInit config

[Simon Yang (Code Review)]

Attention is currently required from: Jamie Chen, Kane Chen.
Simon Yang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60009 )

Change subject: soc/intel/jsl: Add CdClock/SkipCdClockInit config
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Patch Set 7:

(1 comment)

This change is ready for review.

File src/soc/intel/jasperlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/60009/comment/24d0b891_2340ca6b 
PS6, Line 212: 	if (config->SkipCdClockInit) {
> braces {} are not necessary for single statement blocks

fixed