[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel/alderlake: Add support for PCIe speed setting

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85519?usp=email )

Change subject: soc/intel/alderlake: Add support for PCIe speed setting
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soc/intel/alderlake: Add support for PCIe speed setting

This change provides config for devicetree to control PCIe speed

BUG=b:374205496
TEST=build pass

Change-Id: I32a9918a51faa903927a9646605a618744b527c0
Signed-off-by: David Wu 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85519
Tested-by: build bot (Jenkins) 
Reviewed-by: Ren Kuo 
Reviewed-by: Kapil Porwal 
---
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/common/block/include/intelblocks/pcie_rp.h
2 files changed, 29 insertions(+), 0 deletions(-)

Approvals:
  Ren Kuo: Looks good to me, approved
  build bot (Jenkins): Verified
  Kapil Porwal: Looks good to me, approved

diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index d4cbf0f..8a03b05 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -490,6 +490,12 @@
  * |                   | PchPcieL1SubstatesL1_1   |           |           |
  * |                   | PchPcieL1SubstatesL1_1_2 |           | [Default] |
  * |                   | PchPcieL1SubstatesMax    | [Default] |           |
+ * |-------------------|--------------------------|-----------|-----------|
+ * | PchPcieRpPcieSpeed| PchPcieRpPcieSpeedAuto   | [Default] |           |
+ * |                   | PchPcieRpPcieSpeedGen1   |           |           |
+ * |                   | PchPcieRpPcieSpeedGen2   |           |           |
+ * |                   | PchPcieRpPcieSpeedGen3   |           |           |
+ * |                   | PchPcieRpPcieSpeedGen4   |           |           |
  * +-------------------+--------------------------+-----------+-----------+
  */

@@ -527,6 +533,15 @@
    return UPD_INDEX(l1_substates_control);
 }

+static unsigned int adl_pcie_speed_control_to_upd(enum PCIE_SPEED_control pcie_speed_control)
+{
+	/* Use auto unless overwritten */
+	if (!pcie_speed_control)
+		return UPD_INDEX(SPEED_AUTO);
+
+	return UPD_INDEX(pcie_speed_control);
+}
+
 static void configure_pch_rp_power_management(FSP_S_CONFIG *s_cfg,
    				      const struct pcie_rp_config *rp_cfg,
    				      unsigned int index)
@@ -537,6 +552,8 @@
    	adl_aspm_control_to_upd(get_uint_option("pciexp_aspm", rp_cfg->pcie_rp_aspm));
    s_cfg->PcieRpL1Substates[index] =
    	adl_l1ss_control_to_upd(get_uint_option("pciexp_l1ss", rp_cfg->PcieRpL1Substates));
+	s_cfg->PcieRpPcieSpeed[index] =
+		adl_pcie_speed_control_to_upd(get_uint_option("pciexp_speed", rp_cfg->pcie_rp_pcie_speed));
 }

/*
diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
index 7f7dba6..6ff07cf 100644
--- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
+++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
@@ -58,6 +58,16 @@
    ASPM_AUTO,
 };

+/* This enum is for passing into an FSP UPD, typically PCIe Speed */
+enum PCIE_SPEED_control {
+	SPEED_DEFAULT,
+	SPEED_AUTO,
+	SPEED_GEN1,
+	SPEED_GEN2,
+	SPEED_GEN3,
+	SPEED_GEN4,
+};
+
 /* PCIe Root Ports */
 struct pcie_rp_config {
    /* CLKOUT_PCIE_P/N# used by this root port as per schematics. */
@@ -71,6 +81,8 @@
    enum ASPM_control pcie_rp_aspm;
    /* timeout for device detect */
    uint32_t pcie_rp_detect_timeout_ms;
+	/* PCIe RP PCIe Speed */
+	enum PCIE_SPEED_control pcie_rp_pcie_speed;
 };

/*