[coreboot-gerrit] [S] Change in coreboot[master]: soc/intel/common: Add PsysPl1 support

[ChiaLing (Code Review)]

Attention is currently required from: Reka Norman, Ryan Lin, Zhuohao Lee.

ChiaLing has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75678?usp=email )

Change subject: soc/intel/common: Add PsysPl1 support
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Patch Set 4:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/75678/comment/4955a85e_a48f1286 :
PS2, Line 10: More power
            : budget for SOC may be released accordingly.
> This is not true, as discussed in the bug.

Done

File src/soc/intel/common/block/include/intelblocks/power_limit.h:

https://review.coreboot.org/c/coreboot/+/75678/comment/a4138172_719b89d4 :
PS2, Line 39: 	/* Minimum ROP */
            : 	uint16_t min_rop;
> Actually, let's get rid of the min_rop calculation for now. […]

Done