Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48399 )
Change subject: [WIP] plot I/O and roundtrip latency errors ......................................................................
[WIP] plot I/O and roundtrip latency errors
Change-Id: I453e3fe51e4a577f9503350405d9fe4b668bd037 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/48399/1
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 667ec14..3df234a 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1328,6 +1328,9 @@ program_timings(ctrl, channel); test_rcven(ctrl, channel, slotrank);
+ printram("C%dR%d:\t01234567%c\n\t", channel, slotrank, + ctrl->lanes == NUM_LANES ? '8' : ' '); + FOR_ALL_LANES { works[lane] = !does_lane_work(ctrl, channel, slotrank, lane);
@@ -1335,8 +1338,12 @@ some_works = 1; else all_works = 0; + + printram("%c", works[lane] ? '.' : '#'); }
+ printram("\n"); + /* If every lane is working, exit */ if (all_works) return 0;