[coreboot-gerrit] Change in coreboot[master]: nb/intel/haswell: Set up DMI ASPM

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43743 )

Change subject: nb/intel/haswell: Set up DMI ASPM
......................................................................

nb/intel/haswell: Set up DMI ASPM

Tested on Asrock B85M Pro4, still boots.

Change-Id: Ie97ff56eec9f928cfd2d5d43a287f3e0d2fbf3cf
Signed-off-by: Angel Pons 
---
M src/northbridge/intel/haswell/northbridge.c
1 file changed, 38 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/43743/1

diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index ef7742e..4311710 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -418,10 +418,48 @@
    pci_write_config32(host_dev, DEVEN, deven);
 }

+static void northbridge_dmi_init(void)
+{
+	u32 reg32;
+
+	/* Steps prior to DMI ASPM */
+	reg32 = DMIBAR32(0x98);
+	reg32 |= (1 << 6);
+	DMIBAR32(0x98) = reg32;
+
+	reg32 = DMIBAR32(0x22c);
+	reg32 |= (1 << 31);
+	DMIBAR32(0x22c) = reg32;
+
+	reg32 = DMIBAR32(0x238);
+	reg32 |= (1 << 29);
+	DMIBAR32(0x238) = reg32;
+
+	reg32 = DMIBAR32(0xc28);
+	reg32 &= ~0x1f;
+	reg32 |= 0x13;
+	DMIBAR32(0xc28) = reg32;
+
+	/* Clear error status bits */
+	DMIBAR32(0x1c4) = 0xffffffff;
+	DMIBAR32(0x1d0) = 0xffffffff;
+
+	/* Enable ASPM on SA link, should happen before PCH link */
+	reg32 = DMIBAR32(0x88);
+	reg32 |= (1 << 1) | (1 << 0);
+	DMIBAR32(0x88) = reg32;
+
+	/* Enable DMI IOT */
+	DMIBAR8(0xd34) = 0x44;
+}
+
 static void northbridge_init(struct device *dev)
 {
    u8 bios_reset_cpl, pair;

+	if (!CONFIG(INTEL_LYNXPOINT_LP))
+		northbridge_dmi_init();
+
    /* Enable Power Aware Interrupt Routing. */
    pair = MCHBAR8(INTRDIRCTL);
    pair &= ~0x7;	/* Clear 2:0 */