[coreboot-gerrit] [S] Change in coreboot[master]: nb/intel/{sandybridge,haswell}: Generate IOAPIC DMAR entries from hw

[Arthur Heymans (Code Review)]

Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72513 )

Change subject: nb/intel/{sandybridge,haswell}: Generate IOAPIC DMAR entries from hw
......................................................................

nb/intel/{sandybridge,haswell}: Generate IOAPIC DMAR entries from hw

Use acpi_create_dmar_ds_ioapic_from_hw() to generate DMAR entries.

This can restore s3 resume capability for Sandy Bridge platforms lost
after commit d165357ec37c ("sb,soc/intel: Use
register_new_ioapic_gsi0()").

Signed-off-by: Bill XIE 
Change-Id: I83e735707cd9ff30aa339443593239cd7e3e4656
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72513
Reviewed-by: Nico Huber 
Tested-by: build bot (Jenkins) 
Reviewed-by: Arthur Heymans 
---
M src/northbridge/intel/haswell/acpi.c
M src/northbridge/intel/sandybridge/acpi.c
2 files changed, 28 insertions(+), 4 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, but someone else must approve
  Arthur Heymans: Looks good to me, approved

diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c
index 290dc1e..8d179aa 100644
--- a/src/northbridge/intel/haswell/acpi.c
+++ b/src/northbridge/intel/haswell/acpi.c
@@ -4,6 +4,7 @@
 #include <console/console.h>
 #include <commonlib/helpers.h>
 #include <acpi/acpi.h>
+#include <arch/ioapic.h>
 #include <device/device.h>
 #include <device/pci_ops.h>
 #include "haswell.h"
@@ -38,8 +39,9 @@

const unsigned long tmp = current;
    	current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
-		current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS,
-						      PCH_IOAPIC_PCI_SLOT, 0);
+		current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR,
+							      PCH_IOAPIC_PCI_BUS,
+							      PCH_IOAPIC_PCI_SLOT, 0);

size_t i;
    	for (i = 0; i < 8; ++i)
diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c
index c2f6eae..8be161e 100644
--- a/src/northbridge/intel/sandybridge/acpi.c
+++ b/src/northbridge/intel/sandybridge/acpi.c
@@ -4,6 +4,7 @@
 #include <console/console.h>
 #include <commonlib/helpers.h>
 #include <acpi/acpi.h>
+#include <arch/ioapic.h>
 #include <device/device.h>
 #include <device/pci_ops.h>
 #include "sandybridge.h"
@@ -42,8 +43,9 @@
    	const unsigned long tmp = current;
    	current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, VTVC0_BASE);

-		current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS,
-				PCH_IOAPIC_PCI_SLOT, 0);
+		current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR,
+							      PCH_IOAPIC_PCI_BUS,
+							      PCH_IOAPIC_PCI_SLOT, 0);

size_t i;
    	for (i = 0; i < 8; ++i)