Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41900 )
Change subject: soc/amd/common/blocks/xhci: Add an AMD block to generate xHCI ACPI nodes ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/c/coreboot/+/41900/2/src/soc/amd/common/block/xh... File src/soc/amd/common/block/xhci/xhci.c:
https://review.coreboot.org/c/coreboot/+/41900/2/src/soc/amd/common/block/xh... PS2, Line 16: handle_xhci_ext_cap This works fine. But I am curious: Can we not use PORT_CONTROL_CNTR0 and PORT_CONTROL_CNTR1 to extract the number of USB3 and USB2 ports for each controller? Just saves the effort of having to parse the extended capability list.
https://review.coreboot.org/c/coreboot/+/41900/2/src/soc/amd/common/block/xh... PS2, Line 100: lops_pci This can be set to &pci_dev_ops_pci since there is nothing special being done as part of lops_pci.
https://review.coreboot.org/c/coreboot/+/41900/2/src/soc/amd/common/block/xh... PS2, Line 102: };
maybe also handle acpi_name in here too
+1. acpi_name should also be moved to this file.