[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake/include/soc/iomap.h: Add ADL PCH-S reserved spaces

[Michał Żygowski (Code Review)]

Attention is currently required from: Tim Wawrzynczak.
Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63459 )

Change subject: soc/intel/alderlake/include/soc/iomap.h: Add ADL PCH-S reserved spaces
......................................................................

soc/intel/alderlake/include/soc/iomap.h: Add ADL PCH-S reserved spaces

PCH-S maps certain MMIO BARs differently than low power PCHs. The reserved
ranges taken from Intel DOC #630603.

Signed-off-by: Michał Żygowski 
Change-Id: Ifefedc629def207ecd6f7be792f6e12fb6016cc3
---
M src/soc/intel/alderlake/include/soc/iomap.h
1 file changed, 8 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/63459/1

diff --git a/src/soc/intel/alderlake/include/soc/iomap.h b/src/soc/intel/alderlake/include/soc/iomap.h
index 9ff8f54..4f69242 100644
--- a/src/soc/intel/alderlake/include/soc/iomap.h
+++ b/src/soc/intel/alderlake/include/soc/iomap.h
@@ -12,11 +12,19 @@
 /*
  * Memory-mapped I/O registers.
  */
+#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
+#define PCH_PRESERVED_BASE_ADDRESS	0xfe000000
+#define PCH_PRESERVED_BASE_SIZE		0x00800000
+
+#define PCH_TRACE_HUB_BASE_ADDRESS	0xfd800000
+#define PCH_TRACE_HUB_BASE_SIZE		0x00800000
+#else
 #define PCH_PRESERVED_BASE_ADDRESS	0xfc800000
 #define PCH_PRESERVED_BASE_SIZE	0x02000000

#define PCH_TRACE_HUB_BASE_ADDRESS	0xfc800000
 #define PCH_TRACE_HUB_BASE_SIZE	0x00800000
+#endif

#define UART_BASE_SIZE		0x1000