Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43281 )
Change subject: soc/amd/picasso: Drop the inclusion of entry16.ld and reset16.ld ......................................................................
soc/amd/picasso: Drop the inclusion of entry16.ld and reset16.ld
This change drops the inclusion of entry16.ld and reset16.ld instead adds the content of those files directly in memlayout.ld in picasso. This is done to allow the work for top-aligning bootblock to happen independent of Picasso layout. Once that is complete, Picasso layout can be re-evaluated to see if it can make use of the common bootblock linker file includes.
TEST=Verified that coreboot.rom generated using --timeless is the same with and without this change for trembyle.
Change-Id: Ib1218b24a06d0f69b856fb21458a6183fd21fcbc Signed-off-by: Furquan Shaikh furquan@google.com --- M src/soc/amd/picasso/memlayout.ld 1 file changed, 16 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/43281/1
diff --git a/src/soc/amd/picasso/memlayout.ld b/src/soc/amd/picasso/memlayout.ld index 6f43ba1..b7f9167 100644 --- a/src/soc/amd/picasso/memlayout.ld +++ b/src/soc/amd/picasso/memlayout.ld @@ -95,7 +95,20 @@ }
#if ENV_BOOTBLOCK -/* Bootblock specific scripts which provide more SECTION directives. */ -#include <cpu/x86/16bit/entry16.ld> -#include <cpu/x86/16bit/reset16.ld> + +gdtptr16_offset = gdtptr16 & 0xffff; +nullidt_offset = nullidt & 0xffff; + +SECTIONS { + /* Trigger an error if I have an unuseable start address */ + _TOO_LOW = CONFIG_X86_RESET_VECTOR - 0xfff0; + _bogus = ASSERT(_start16bit >= _TOO_LOW, "_start16bit too low. Please report."); + + . = CONFIG_X86_RESET_VECTOR; + .reset . : { + *(.reset); + . = 15; + BYTE(0x00); + } +} #endif /* ENV_BOOTBLOCK */